158 lines
6.1 KiB
ArmAsm
158 lines
6.1 KiB
ArmAsm
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2006,2007 by Greg White
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include "config.h"
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#include "cpu.h"
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/* TTB routines not used */
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/** Cache coherency **/
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#if 0 /* unused */
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/*
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* Write DCache back to RAM for the given range and remove cache lines
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* from DCache afterwards
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* void commit_discard_dcache_range(const void *base, unsigned int size);
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*/
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.section .text.commit_discard_dcache_range, "ax", %progbits
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.align 2
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.global commit_discard_dcache_range
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.type commit_discard_dcache_range, %function
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@ MVA format: 31:5 = Modified virtual address, 4:0 = SBZ
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commit_discard_dcache_range:
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add r1, r0, r1 @ size -> end
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cmp r1, r0 @ end <= start?
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subhi r1, r1, #1 @ round it down
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movhi r2, #0 @
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mcrrhi p15, 0, r1, r0, c14 @ Clean and invalidate DCache range
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mcrhi p15, 0, r2, c7, c10, 4 @ Data synchronization barrier
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bx lr @
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.size commit_discard_dcache_range, .-commit_discard_dcache_range
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#endif /* unused function */
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/*
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* Write DCache back to RAM for the given range
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* void commit_dcache_range(const void *base, unsigned int size);
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*/
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.section .text.commit_dcache_range, "ax", %progbits
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.align 2
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.global commit_dcache_range
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.type commit_dcache_range, %function
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@ MVA format: 31:5 = Modified virtual address, 4:0 = SBZ
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commit_dcache_range:
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add r1, r0, r1 @ size -> end
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cmp r1, r0 @ end <= start?
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subhi r1, r1, #1 @ round it down
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movhi r2, #0 @
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mcrrhi p15, 0, r1, r0, c12 @ Clean DCache range
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mcrhi p15, 0, r2, c7, c10, 4 @ Data synchronization barrier
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bx lr @
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.size commit_dcache_range, .-commit_dcache_range
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/*
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* Remove cache lines for the given range from DCache
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* will *NOT* do write back except for buffer edges not on a line boundary
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* void discard_dcache_range(const void *base, unsigned int size);
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*/
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.section .text.discard_dcache_range, "ax", %progbits
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.align 2
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.global discard_dcache_range
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.type discard_dcache_range, %function
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@ MVA format: 31:5 = Modified virtual address, 4:0 = SBZ
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discard_dcache_range:
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add r1, r0, r1 @ size -> end
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cmp r1, r0 @ end <= start?
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bxls lr @
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tst r0, #31 @ Check first line for bits set
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bicne r0, r0, #31 @ Clear low five bits (down)
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mcrne p15, 0, r0, c7, c14, 1 @ Clean and invalidate line by MVA
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@ if not cache aligned
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addne r0, r0, #32 @ Move to the next cache line
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@
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tst r1, #31 @ Check last line for bits set
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bicne r1, r1, #31 @ Clear low five bits (down)
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mcrne p15, 0, r1, c7, c14, 1 @ Clean and invalidate line by MVA
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@ if not cache aligned
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sub r1, r1, #32 @ Move to the previous cache line
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cmp r1, r0 @ end < start now?
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mcrrhs p15, 0, r1, r0, c6 @ Invalidate DCache range
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mov r0, #0 @
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mcr p15, 0, r0, c7, c10, 4 @ Data synchronization barrier
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bx lr @
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.size discard_dcache_range, .-discard_dcache_range
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/*
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* Write entire DCache back to RAM
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* void commit_dcache(void);
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*/
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.section .text.commit_dcache, "ax", %progbits
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.align 2
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.global commit_dcache
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.type commit_dcache, %function
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commit_dcache:
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mov r0, #0 @
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mcr p15, 0, r0, c7, c10, 0 @ Clean entire DCache
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mcr p15, 0, r0, c7, c10, 4 @ Data synchronization barrier
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bx lr @
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.size commit_dcache, .-commit_dcache
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/*
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* Clean and invalidate entire DCache, will do writeback
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* void commit_discard_dcache(void);
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*/
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.section .icode.commit_discard_dcache, "ax", %progbits
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.align 2
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.global commit_discard_dcache
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.type commit_discard_dcache, %function
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commit_discard_dcache:
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mov r0, #0 @
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mcr p15, 0, r0, c7, c14, 0 @ Clean and invalidate entire DCache
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mcr p15, 0, r0, c7, c10, 4 @ Data synchronization barrier
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bx lr @
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.size commit_discard_dcache, .-commit_discard_dcache
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/*
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* Discards the entire ICache, and commit+discards the entire DCache
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* void commit_discard_idcache(void);
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*/
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.section .icode.commit_discard_idcache, "ax", %progbits
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.align 2
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.global commit_discard_idcache
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.type commit_discard_idcache, %function
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commit_discard_idcache:
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mov r0, #0 @
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mcr p15, 0, r0, c7, c14, 0 @ Clean and invalidate entire DCache
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mcr p15, 0, r0, c7, c5, 0 @ Invalidate entire ICache
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@ Also flushes the branch target cache
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mcr p15, 0, r0, c7, c10, 4 @ Data synchronization barrier
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mcr p15, 0, r0, c7, c5, 4 @ Flush prefetch buffer (IMB)
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bx lr @
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.size commit_discard_idcache, .-commit_discard_idcache
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