424 lines
18 KiB
C
424 lines
18 KiB
C
#include <stdio.h>
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#include <string.h>
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#include <stdint.h>
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#define ULONG uint32_t
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#define UCHAR uint8_t
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#define FRMT "0x%x" // "0x%x"
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#define SHFTFRMC "%s %s #%d" // "%s %s %d"
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#define SHFTFRMR "%s %s %s" // "%s %s %s"
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//#define FRMT "0x%x"
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//#define SHFTFRMC "%s %s %d"
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//#define SHFTFRMR "%s %s %s"
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char *cond[16] = { "eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc", "hi", "ls", "ge", "lt", "gt", "le", "", "nv" };
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char *cnd1[16] = { "eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc", "hi", "ls", "ge", "lt", "gt", "le", " ", "nv" };
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char *opcd[16] = {"and","eor","sub","rsb","add","adc","sbc","rsc","tst","teq","cmp","cmn","orr","mov","bic","mvn" };
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char setc[32] = {0,115,0,115,0,115,0,115,0,115,0,115,0,115,0,115,0, 0 ,0, 0 ,0, 0 ,0, 0 ,0,115,0,115,0,115,0,115 };
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char *regs[16] = { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "sl", "fp", "ip", "sp", "lr", "pc" };
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char *shfts[4] = { "lsl", "lsr", "asr", "ror" };
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/*
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31-28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
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Cond 0 0 I ---Opcode--- S |----Rn----- ----Rd----- --------Operand 2-------- Data Processing /PSR Transfer
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Cond 0 0 0 0 | 0 0 A S |----Rd----- ----Rn----- ---Rs---- 1 0 0 1 --Rm--- Multiply
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Cond 0 0 0 0 | 1 U A S |---RdHi---- ---RdLo---- ---Rn---- 1 0 0 1 --Rm--- Multiply Long
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Cond 0 0 0 1 | 0 B 0 0 |----Rn----- ----Rd----- 0 0 0 0 1 0 0 1 --Rm--- Single Data Swap
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Cond 0 0 0 1 | 0 0 1 0 |1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 --Rn--- Branch and Exchange
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Cond 0 0 0 P | U 0 W L |----Rn----- ----Rd----- 0 0 0 0 1 S H 1 --Rm--- Halfword Data Transfer: register offset
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Cond 0 0 0 P | U 1 W L |----Rn----- ----Rd----- --Offset- 1 S H 1 -Offset Halfword Data Transfer: immediate offset
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Cond 0 1 I P | U B W L |----Rn----- ----Rd----- --------Offset----------- Single Data Transfer
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Cond 0 1 1 1 | x x x x |x x x x x x x x x x x x x x x 1 x x x x Undefined
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Cond 1 0 0 P | U S W L |----Rn----- -----------Register List------------- Block Data Transfer
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Cond 1 0 1 L | -------------------------Offset------------------------------ Branch
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Cond 1 1 0 P | U N W L |----Rn----- ----CRd---- ---CP#--- -----Offset---- Coprocessor Data Transfer
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Cond 1 1 1 0 | --CP Opc---|----CRn---- ----CRd---- ---CP#--- -CP-- 0 --CRm-- Coprocessor Data Operation
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Cond 1 1 1 0 | CP Opc L |----CRn---- ----Rd----- ---CP#--- -CP-- 1 --CRm-- Coprocessor Register Transfer
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Cond 1 1 1 1 | x x x x |x x x x x x x x x x x x x x x x x x x x Software Interrupt
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0x04200000
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0001 0 0 0 0 0 1 1 0 6 e 1 1 1 0 1 8
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================================================================================
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Cond 0 1 I P | U B W L |----Rn----- ----Rd----- --------Offset----------- Single Data Transfer
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EQ 0 Z set equal
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NE 1 Z clear not equal
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CS 2 C set unsigned higher or same
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CC 3 C clear unsigned lower
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MI 4 N set negative
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PL 5 N clear positive or zero
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VS 6 V set overflow
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VC 7 V clear no overflow
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HI 8 C set and Z clear unsigned higher
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LS 9 C clear or Z set unsigned lower or same
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GE A N equals V greater or equal
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LT B N not equal to V less than
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GT C Z clear AND (N equals V) greater than
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LE D Z set OR (N not equal to V) less than or equal
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AL E (ignored) always
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AND 0 operand1 AND operand2
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EOR 1 operand1 EOR operand2
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SUB 2 operand1 - operand2
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RSB 3 operand2 - operand1
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ADD 4 operand1 + operand2
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ADC 5 operand1 + operand2 + carry
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SBC 6 operand1 - operand2 + carry - 1
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RSC 7 operand2 - operand1 + carry - 1
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TST 8 AND, but result is not written
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TEQ 9 as EOR, but result is not written
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CMP A as SUB, but result is not written
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CMN B as ADD, but result is not written
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ORR C operand1 OR operand2
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MOV D operand2 (operand1 is ignored)
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BIC E operand1 AND NOT operand2 (Bit clear)
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MVN F NOT operand2 (operand1 is ignored)
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*/
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void multiply_stg(char *stg, ULONG val)
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{
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if((val&0xc00000) == 0) // simple mul
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{
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if(val & 0x100000) // set condition flags
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if(val & 0x200000) sprintf(stg+strlen(stg), "mla%ss ", cond[val>>28]);
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else sprintf(stg+strlen(stg), "mul%ss ", cond[val>>28]);
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else
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if(val & 0x200000) sprintf(stg+strlen(stg), "mla%s ", cnd1[val>>28]);
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else sprintf(stg+strlen(stg), "mul%s ", cnd1[val>>28]);
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if(val & 0x200000) // accumulate
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sprintf(stg+strlen(stg), "%s, %s, %s, %s", regs[(val>>16)&15], regs[(val>>0)&15], regs[(val>>8)&15], regs[(val>>12)&15]);
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else
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sprintf(stg+strlen(stg), "%s, %s, %s", regs[(val>>16)&15], regs[(val>>0)&15], regs[(val>>8)&15]);
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}
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else
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{
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if(val & 0x100000) // set condition flags
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if(val & 0x200000) // accumulate
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if(val & 0x400000) sprintf(stg+strlen(stg), "smlal%ss ", cond[val>>28]);
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else sprintf(stg+strlen(stg), "umlal%ss ", cond[val>>28]);
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else
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if(val & 0x400000) sprintf(stg+strlen(stg), "smull%ss ", cond[val>>28]);
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else sprintf(stg+strlen(stg), "umull%ss ", cond[val>>28]);
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else
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if(val & 0x200000)
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if(val & 0x400000) sprintf(stg+strlen(stg), "smlal%s ", cond[val>>28]);
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else sprintf(stg+strlen(stg), "umlal%s ", cond[val>>28]);
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else
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if(val & 0x400000) sprintf(stg+strlen(stg), "smull%s ", cond[val>>28]);
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else sprintf(stg+strlen(stg), "umull%s ", cond[val>>28]);
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sprintf(stg+strlen(stg), "%s, %s, %s, %s", regs[(val>>12)&15], regs[(val>>16)&15], regs[(val>>0)&15], regs[(val>>8)&15]);
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}
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}
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void halfword_stg(char *stg, ULONG val)
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{
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ULONG off = ((val>>4) & 0xf0) + (val & 0x0f);
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if(val & 0x100000) sprintf(stg+strlen(stg), "ldr%s", cond[val>>28]);
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else sprintf(stg+strlen(stg), "str%s", cond[val>>28]);
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switch((val>>5) & 3) // SWP, HW, SB, SH
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{
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case 0: sprintf(stg+strlen(stg), "error: SWP"); break;
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case 1: sprintf(stg+strlen(stg), "h "); break;
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case 2: sprintf(stg+strlen(stg), "sb "); break;
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case 3: sprintf(stg+strlen(stg), "sh "); break;
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}
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if(val & 0x400000) // immidiate offset
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if(val & 0x1000000) // pre index
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if(val & 0x200000) // write back
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if(val & 0x800000) sprintf(stg+strlen(stg), "%s, [%s, "FRMT"]!", regs[(val>>12)&15], regs[(val>>16)&15], off);
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else sprintf(stg+strlen(stg), "%s, [%s, -"FRMT"]!", regs[(val>>12)&15], regs[(val>>16)&15], off);
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else
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if(val & 0x800000) sprintf(stg+strlen(stg), "%s, [%s, "FRMT"]", regs[(val>>12)&15], regs[(val>>16)&15], off);
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else sprintf(stg+strlen(stg), "%s, [%s, -"FRMT"]", regs[(val>>12)&15], regs[(val>>16)&15], off);
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else
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if(val & 0x200000) // write back
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sprintf(stg+strlen(stg), "error 'write back' on post indexed");
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else
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if(val & 0x800000) sprintf(stg+strlen(stg), "%s, [%s], "FRMT, regs[(val>>12)&15], regs[(val>>16)&15], off);
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else sprintf(stg+strlen(stg), "%s, [%s], -"FRMT, regs[(val>>12)&15], regs[(val>>16)&15], off);
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else
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if(val & 0x1000000) // pre index
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if(val & 0x200000) // write back
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if(val & 0x800000) sprintf(stg+strlen(stg), "%s, [%s, %s]!", regs[(val>>12)&15], regs[(val>>16)&15], regs[val&15]);
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else sprintf(stg+strlen(stg), "%s, [%s, -%s]!", regs[(val>>12)&15], regs[(val>>16)&15], regs[val&15]);
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else
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if(val & 0x800000) sprintf(stg+strlen(stg), "%s, [%s, %s]", regs[(val>>12)&15], regs[(val>>16)&15], regs[val&15]);
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else sprintf(stg+strlen(stg), "%s, [%s, -%s]", regs[(val>>12)&15], regs[(val>>16)&15], regs[val&15]);
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else
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if(val & 0x200000) // write back
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sprintf(stg+strlen(stg), "error 'write back' on post indexed");
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else
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if(val & 0x800000) sprintf(stg+strlen(stg), "%s, [%s], %s", regs[(val>>12)&15], regs[(val>>16)&15], regs[val&15]);
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else sprintf(stg+strlen(stg), "%s, [%s], -%s", regs[(val>>12)&15], regs[(val>>16)&15], regs[val&15]);
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}
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void branch_stg(char *stg, ULONG val, ULONG pos)
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{
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ULONG off = pos + (((int32_t)val << 8) >> 6) + 8;
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if((val & 0x0ffffff0) == 0x012fff10) // bx instruction
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{ sprintf(stg+strlen(stg), "bx%s %s", cond[val>>28], regs[val&15]); }
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else
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{
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if(((val>>24)&15) == 10) sprintf(stg+strlen(stg), "b%s ", cond[val>>28]);
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else sprintf(stg+strlen(stg), "bl%s ", cond[val>>28]);
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sprintf(stg+strlen(stg), "0x%x", off);
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}
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}
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void opcode_stg(char *stg, ULONG val, ULONG off)
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{
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ULONG des, op1;
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char op2[80];
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char *st = stg + strlen(stg);
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if(((val & 0x0ffffff0) == 0x012fff10) && (val & 16))
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{ branch_stg(stg, val, off); return; }
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else if(((val & 0x0f000000) == 0x00000000) && ((val & 0xf0) == 0x90))
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{ multiply_stg(stg, val); return; }
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else if(((val & 0x0f000000) <= 0x01000000) && ((val & 0x90) == 0x90) && ((val & 0xf0) > 0x90) && ((val & 0x01200000) != 0x00200000))
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{ halfword_stg(stg, val); return; }
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sprintf(stg+strlen(stg), "%s%s%s ", opcd[(val>>21) & 15], cond[val>>28], setc[(val>>20) & 31]?"s":" ");
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des = (val>>12) & 15;
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op1 = (val>>16) & 15;
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if(val & 0x2000000) // immidiate
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{
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off = (ULONG)((uint64_t)(val&0xff) << (32 - 2 * ((val >> 8) & 15))) | ((val&0xff) >> 2 * ((val >> 8) & 15));
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sprintf(op2, FRMT" ", off);
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}
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else
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{
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if(val & 16) // shift type
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sprintf(op2, SHFTFRMR, regs[val&15], shfts[(val>>5)&3], regs[(val>>8)&15]);
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else
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if((val>>7) & 31)
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sprintf(op2, SHFTFRMC, regs[val&15], shfts[(val>>5)&3], (val>>7) & 31);
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else
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sprintf(op2, "%s ", regs[val&15]);
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}
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switch((val>>21) & 15)
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{
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case 0: case 1: case 2: case 3: case 4: case 5: case 6: case 7: case 12:
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case 14: sprintf(stg+strlen(stg), "%s, %s, %s", regs[des], regs[op1], op2); break;
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case 8: case 9: case 10:
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case 11: if(val & 0x100000) // set status
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sprintf(stg+strlen(stg), "%s, %s", regs[op1], op2); // standard TEQ,TST,CMP,CMN
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else
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{ //special MRS/MSR opcodes
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if((((val>>23) & 31) == 2) && ((val & 0x3f0fff) == 0x0f0000))
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{ sprintf(st, "mrs%s %s, %s", cnd1[val>>28], regs[des], val&0x400000?"SPSR_xx":"CPSR"); }
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else
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if((((val>>23) & 31) == 2) && ((val & 0x30fff0) == 0x20f000))
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{ sprintf(st, "msr%s %s, %s", cnd1[val>>28], val&0x400000?"SPSR_xx":"CPSR", regs[val&15]); }
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else
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if((((val>>23) & 31) == 6) && ((val & 0x30f000) == 0x20f000))
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{ sprintf(st, "msr%s %s, %s", cnd1[val>>28], val&0x400000?"SPSR_xx":"CPSR_cf", op2); }
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else
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if((((val>>23) & 31) == 2) && ((val & 0x300ff0) == 0x000090))
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{ sprintf(st, "swp%s%s %s, %s, [%s]", val&0x400000?"b":"", cnd1[val>>28], regs[(val>>12)&15], regs[val&15], regs[(val>>16)&15]); }
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else
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{ sprintf(stg+strlen(stg), "??????????????"); }
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} break;
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case 13:
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case 15: sprintf(stg+strlen(stg), "%s, %s", regs[des], op2); break;
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}
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}
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void opcode_cop(char *stg, ULONG val, ULONG off)
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{
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char* op;
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int opcode1 = (val >> 21) & 0x7;
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int CRn = (val >> 16) & 0xf;
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int Rd = (val >> 12) & 0xf;
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int cp_num = (val >> 8) & 0xf;
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int opcode2 = (val >> 5) & 0x7;
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int CRm = val & 0xf;
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// ee073f5e mcr 15, 0, r3, cr7, cr14, {2}
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if (val & (1<<4)) {
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if (val & (1<<20)) {
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op = "mrc";
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} else {
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op = "mcr";
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}
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opcode1 = (val >> 21) & 0x7;
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CRn = (val >> 16) & 0xf;
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Rd = (val >> 12) & 0xf;
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cp_num = (val >> 8) & 0xf;
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opcode2 = (val >> 5) & 0x7;
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CRm = val & 0xf;
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sprintf(stg+strlen(stg), "%s%s %d, %d, r%d, cr%d, cr%d, {%d}", op, cnd1[val>>28], cp_num, opcode1, Rd, CRn, CRm, opcode2);
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} else {
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op = "cdp";
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opcode1 = (val >> 20) & 0xf;
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CRn = (val >> 16) & 0xf;
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Rd = (val >> 12) & 0xf;
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cp_num = (val >> 8) & 0xf;
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opcode2 = (val >> 5) & 0x7;
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CRm = val & 0xf;
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sprintf(stg+strlen(stg), "%s%s %d, %d, cr%d, cr%d, cr%d, {%d}", op, cnd1[val>>28], cp_num, opcode1, Rd, CRn, CRm, opcode2);
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}
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}
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void single_data(char *stg, ULONG val)
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{
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char op2[80];
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if(((val & 0x0e000000) == 0x06000000) && (val & 16))
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{ sprintf(stg+strlen(stg), "undef%s", cond[val>>28]);
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return;
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}
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if(val & 0x400000)
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if(val & 0x100000) sprintf(stg+strlen(stg), "ldr%sb ", cond[val>>28]);
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else sprintf(stg+strlen(stg), "str%sb ", cond[val>>28]);
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else
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if(val & 0x100000) sprintf(stg+strlen(stg), "ldr%s ", cnd1[val>>28]);
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else sprintf(stg+strlen(stg), "str%s ", cnd1[val>>28]);
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if(val & 0x2000000) {// reg offset
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if(val & 16) // shift type
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sprintf(op2, "error: reg defined shift");
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else
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if((val>>7) & 31)
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sprintf(op2, SHFTFRMC, regs[val&15], shfts[(val>>5)&3], (val>>7) & 31);
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else
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sprintf(op2, "%s", regs[val&15]);
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}
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if(val & 0x2000000) // reg offset
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if(val & 0x1000000) // pre index
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if(val & 0x800000) // up offset (+)
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if(val & 0x200000) // write back
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sprintf(stg+strlen(stg), "%s, [%s, %s]!", regs[(val>>12)&15], regs[(val>>16)&15], op2);
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else
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sprintf(stg+strlen(stg), "%s, [%s, %s]", regs[(val>>12)&15], regs[(val>>16)&15], op2);
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else
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if(val & 0x200000) // write back
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sprintf(stg+strlen(stg), "%s, [%s, -%s]!", regs[(val>>12)&15], regs[(val>>16)&15], op2);
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else
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sprintf(stg+strlen(stg), "%s, [%s, -%s]", regs[(val>>12)&15], regs[(val>>16)&15], op2);
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else
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if(val & 0x200000) // write back
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sprintf(stg+strlen(stg), "error 'write back' set");
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else
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if(val & 0x800000) // up offset (+)
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sprintf(stg+strlen(stg), "%s, [%s], %s", regs[(val>>12)&15], regs[(val>>16)&15], op2);
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else
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sprintf(stg+strlen(stg), "%s, [%s], -%s", regs[(val>>12)&15], regs[(val>>16)&15], op2);
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else
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if(val & 0x1000000) // pre index
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if(val & 0x800000) // up offset (+)
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if(val & 0x200000) // write back
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if(val & 0xfff) sprintf(stg+strlen(stg), "%s, [%s, "FRMT"]!", regs[(val>>12)&15], regs[(val>>16)&15], val & 0xfff);
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else sprintf(stg+strlen(stg), "%s, [%s]!", regs[(val>>12)&15], regs[(val>>16)&15]);
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else
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if(val & 0xfff) sprintf(stg+strlen(stg), "%s, [%s, "FRMT"]", regs[(val>>12)&15], regs[(val>>16)&15], val & 0xfff);
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else sprintf(stg+strlen(stg), "%s, [%s]", regs[(val>>12)&15], regs[(val>>16)&15]);
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else
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if(val & 0x200000) // write back
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if(val & 0xfff) sprintf(stg+strlen(stg), "%s, [%s, -"FRMT"]!", regs[(val>>12)&15], regs[(val>>16)&15], val & 0xfff);
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else sprintf(stg+strlen(stg), "%s, [%s]!", regs[(val>>12)&15], regs[(val>>16)&15]);
|
|
else
|
|
if(val & 0xfff) sprintf(stg+strlen(stg), "%s, [%s, -"FRMT"]", regs[(val>>12)&15], regs[(val>>16)&15], val & 0xfff);
|
|
else sprintf(stg+strlen(stg), "%s, [%s]", regs[(val>>12)&15], regs[(val>>16)&15]);
|
|
else
|
|
if(val & 0x200000) // write back
|
|
sprintf(stg+strlen(stg), "error 'write back' set");
|
|
else
|
|
if(val & 0x800000) // up offset (+)
|
|
if(val & 0xfff) sprintf(stg+strlen(stg), "%s, [%s], "FRMT, regs[(val>>12)&15], regs[(val>>16)&15], val & 0xfff);
|
|
else sprintf(stg+strlen(stg), "%s, [%s]", regs[(val>>12)&15], regs[(val>>16)&15]);
|
|
else
|
|
if(val & 0xfff) sprintf(stg+strlen(stg), "%s, [%s], -"FRMT, regs[(val>>12)&15], regs[(val>>16)&15], val & 0xfff);
|
|
else sprintf(stg+strlen(stg), "%s, [%s]", regs[(val>>12)&15], regs[(val>>16)&15]);
|
|
}
|
|
|
|
void block_data(char *stg, ULONG val)
|
|
{
|
|
char lst[80];
|
|
int i;
|
|
|
|
strcpy(lst, "{");
|
|
for(i=0; i<16; i++)
|
|
if(val & (1<<i))
|
|
sprintf(lst+strlen(lst), "%s, ", regs[i]);
|
|
if(strlen(lst)>2)
|
|
strcpy(lst+strlen(lst)-2, "}");
|
|
else
|
|
strcpy(lst+strlen(lst), "}");
|
|
|
|
if(val & 0x400000) // load psr or force user mode
|
|
strcpy(lst+strlen(lst), "^");
|
|
|
|
|
|
if(val & 0x100000) // load
|
|
if(val & 0x1000000) // pre offset
|
|
if(val & 0x800000) sprintf(stg+strlen(stg), "ldm%sib ", cond[val>>28]);
|
|
else sprintf(stg+strlen(stg), "ldm%sdb ", cond[val>>28]);
|
|
else
|
|
if(val & 0x800000) sprintf(stg+strlen(stg), "ldm%sia ", cond[val>>28]);
|
|
else sprintf(stg+strlen(stg), "ldm%sda ", cond[val>>28]);
|
|
else
|
|
if(val & 0x1000000)
|
|
if(val & 0x800000) sprintf(stg+strlen(stg), "stm%sib ", cond[val>>28]);
|
|
else sprintf(stg+strlen(stg), "stm%sdb ", cond[val>>28]);
|
|
else
|
|
if(val & 0x800000) sprintf(stg+strlen(stg), "stm%sia ", cond[val>>28]);
|
|
else sprintf(stg+strlen(stg), "stm%sda ", cond[val>>28]);
|
|
|
|
switch((val>>21)&3)
|
|
{
|
|
case 0: sprintf(stg+strlen(stg), "%s, %s", regs[(val>>16)&15], lst); break;
|
|
case 1: sprintf(stg+strlen(stg), "%s!, %s", regs[(val>>16)&15], lst); break;
|
|
case 2: sprintf(stg+strlen(stg), "%s, %s", regs[(val>>16)&15], lst); break;
|
|
case 3: sprintf(stg+strlen(stg), "%s!, %s", regs[(val>>16)&15], lst); break;
|
|
}
|
|
}
|
|
|
|
void dis_asm(ULONG off, ULONG val, char *stg)
|
|
{
|
|
sprintf(stg, "%6x: %08x ", off, val);
|
|
|
|
switch((val >> 24) & 15)
|
|
{
|
|
case 0:
|
|
case 1:
|
|
case 2:
|
|
case 3: opcode_stg(stg, val, off); break;
|
|
case 4:
|
|
case 5:
|
|
case 6:
|
|
case 7: single_data(stg, val); break;
|
|
case 8:
|
|
case 9: block_data(stg, val); break;
|
|
case 10:
|
|
case 11: branch_stg(stg, val, off); break;
|
|
case 12:
|
|
case 13: sprintf(stg+strlen(stg), "cop%s", cnd1[val>>28]); break;
|
|
case 14: opcode_cop(stg, val, off); break;
|
|
case 15: sprintf(stg+strlen(stg), "swi%s", cnd1[val>>28]); break;
|
|
}
|
|
}
|