333 lines
8.0 KiB
ArmAsm
333 lines
8.0 KiB
ArmAsm
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2008 by Maurus Cuelenaere
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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/*
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* init.S
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*
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* Initialization code for JzRISC.
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*
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* Author: Seeger Chin
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* e-mail: seeger.chin@gmail.com
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*
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* Copyright (C) 2006 Ingenic Semiconductor Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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*/
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#include "config.h"
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#include "mips.h"
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.text
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.extern system_main
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.extern main
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.global _start
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.section .init.text
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.set mips32
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.set noreorder
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.set noat
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#ifdef BOOTLOADER
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#ifndef XDUOO_X3
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/* These will get filled in by scramble */
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.word 0 /* Empty */
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.word 0 /* Filesize */
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/* Relocate bootloader */
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la t0, (_loadaddress-0xE00000)
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la t1, _loadaddress
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la t2, _bootend
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_relocate_loop:
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lw t3, 0(t0)
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addiu t1, 4
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addiu t0, 4
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bne t1, t2, _relocate_loop
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sw t3, -4(t1)
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#endif
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#endif
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_start:
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la ra, _start
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/*
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----------------------------------------------------
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Init CP0 registers.
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----------------------------------------------------
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*/
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mtc0 zero, C0_WATCHLO
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mtc0 zero, C0_WATCHHI
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li t0, (M_StatusBEV | M_StatusIM7 | M_StatusIM6 \
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| M_StatusIM5 | M_StatusIM4 | M_StatusIM3 \
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| M_StatusIM2 | M_StatusERL)
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/*
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BEV = Enable Boot Exception Vectors
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IMx = Interrupt mask
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ERL = Denotes error level
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*/
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mtc0 t0, C0_STATUS
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li t0, M_CauseIV
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mtc0 t0, C0_CAUSE
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/*
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----------------------------------------------------
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Init caches, assumes a 4way*128set*32byte I/D cache
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----------------------------------------------------
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*/
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li t0, 3 # enable cache for kseg0 accesses
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mtc0 t0, C0_CONFIG # CONFIG reg
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la t0, 0x80000000 # an idx op should use an unmappable address
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ori t1, t0, 0x4000 # 16kB cache
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mtc0 zero, C0_TAGLO # TAGLO reg
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mtc0 zero, C0_TAGHI # TAGHI reg
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_cache_loop:
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cache 0x8, 0(t0) # index store icache tag
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cache 0x9, 0(t0) # index store dcache tag
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addiu t0, t0, 0x20 # 32 bytes per cache line
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bne t0, t1, _cache_loop
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nop
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/*
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----------------------------------------------------
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Invalidate BTB
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----------------------------------------------------
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*/
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mfc0 t0, C0_CONFIG
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nop
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ori t0, 2
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mtc0 t0, C0_CONFIG
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nop
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/*
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----------------------------------------------------
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Copy IRAM section
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* copy IRAM first before BSS gets cleared, as both
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have the same address
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----------------------------------------------------
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*/
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la t0, _iramcopy
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la t1, _iramstart
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la t2, _iramend
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_iram_loop:
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lw t3, 0(t0)
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addiu t1, 4
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addiu t0, 4
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bne t1, t2, _iram_loop
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sw t3, -4(t1)
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/*
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----------------------------------------------------
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Clear BSS section
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----------------------------------------------------
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*/
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la t0, _edata
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la t1, _end
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_bss_loop:
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addiu t0, 4
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bne t0, t1, _bss_loop
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sw zero, -4(t0)
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/*
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----------------------------------------------------
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Set up stack
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----------------------------------------------------
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*/
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la sp, stackend
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la t0, stackbegin
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li t2, 0xDEADBEEF
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_stack_loop:
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addiu t0, 4
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bne t0, sp, _stack_loop
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sw t2, -4(t0)
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/*
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----------------------------------------------------
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Jump to C code
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----------------------------------------------------
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*/
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jal system_main /* Init clocks etc first */
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nop
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j main
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nop
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/*
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* 0x0 - Simple TLB refill handler
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* 0x100 - Cache error handler
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* 0x180 - Exception/Interrupt handler
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* 0x200 - Special Exception Interrupt handler (when IV is set in CP0_CAUSE)
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*/
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.section .vectors.1, "ax", %progbits
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j tlb_refill_handler
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nop
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.section .vectors.2, "ax", %progbits
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j real_exception_handler
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nop
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.section .vectors.3, "ax", %progbits
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j real_exception_handler
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nop
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.section .vectors.4, "ax", %progbits
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j real_exception_handler
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nop
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.section .vectors, "ax", %progbits
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real_exception_handler:
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addiu sp, -0x80
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sw ra, 0(sp)
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sw fp, 4(sp)
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sw gp, 8(sp)
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sw t9, 0xC(sp)
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sw t8, 0x10(sp)
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sw s7, 0x14(sp)
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sw s6, 0x18(sp)
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sw s5, 0x1C(sp)
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sw s4, 0x20(sp)
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sw s3, 0x24(sp)
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sw s2, 0x28(sp)
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sw s1, 0x2C(sp)
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sw s0, 0x30(sp)
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sw t7, 0x34(sp)
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sw t6, 0x38(sp)
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sw t5, 0x3C(sp)
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sw t4, 0x40(sp)
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sw t3, 0x44(sp)
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sw t2, 0x48(sp)
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sw t1, 0x4C(sp)
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sw t0, 0x50(sp)
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sw a3, 0x54(sp)
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sw a2, 0x58(sp)
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sw a1, 0x5C(sp)
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sw a0, 0x60(sp)
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sw v1, 0x64(sp)
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sw v0, 0x68(sp)
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sw $1, 0x6C(sp)
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mflo k0
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nop
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sw k0, 0x70(sp)
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mfhi k0
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nop
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sw k0, 0x74(sp)
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mfc0 k0, C0_STATUS
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sll zero, 1
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sll zero, 1
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sll zero, 1
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sll zero, 1
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sw k0, 0x78(sp)
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mfc0 k0, C0_EPC
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sll zero, 1
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sll zero, 1
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sll zero, 1
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sll zero, 1
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sw k0, 0x7C(sp)
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li k1, M_CauseExcCode
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mfc0 k0, C0_CAUSE
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and k0, k1
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beq zero, k0, _int
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nop
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j _exception
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nop
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_int:
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jal intr_handler
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nop
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j _exception_return
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_exception:
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move a0, sp
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mfc0 a1, C0_CAUSE
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sll zero, 1
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sll zero, 1
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sll zero, 1
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sll zero, 1
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mfc0 a2, C0_EPC
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sll zero, 1
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sll zero, 1
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sll zero, 1
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sll zero, 1
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jal exception_handler
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nop
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_exception_return:
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lw ra, 0(sp)
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lw fp, 4(sp)
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lw gp, 8(sp)
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lw t9, 0xC(sp)
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lw t8, 0x10(sp)
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lw s7, 0x14(sp)
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lw s6, 0x18(sp)
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lw s5, 0x1C(sp)
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lw s4, 0x20(sp)
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lw s3, 0x24(sp)
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lw s2, 0x28(sp)
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lw s1, 0x2C(sp)
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lw s0, 0x30(sp)
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lw t7, 0x34(sp)
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lw t6, 0x38(sp)
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lw t5, 0x3C(sp)
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lw t4, 0x40(sp)
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lw t3, 0x44(sp)
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lw t2, 0x48(sp)
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lw t1, 0x4C(sp)
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lw t0, 0x50(sp)
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lw a3, 0x54(sp)
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lw a2, 0x58(sp)
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lw a1, 0x5C(sp)
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lw a0, 0x60(sp)
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lw v1, 0x64(sp)
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lw v0, 0x68(sp)
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lw $1, 0x6C(sp)
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lw k0, 0x70(sp)
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mtlo k0
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nop
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lw k0, 0x74(sp)
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mthi k0
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nop
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lw k0, 0x78(sp)
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mtc0 k0, C0_STATUS
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nop
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sll zero, 1
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sll zero, 1
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sll zero, 1
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sll zero, 1
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lw k0, 0x7C(sp)
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mtc0 k0, C0_EPC
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nop
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sll zero, 1
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sll zero, 1
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sll zero, 1
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sll zero, 1
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addiu sp, 0x80
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eret
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nop
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.set reorder
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.set at
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