536 lines
16 KiB
C
536 lines
16 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2008 by Maurus Cuelenaere
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include "config.h"
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#include "jz4740.h"
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#include "mips.h"
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#include "mmu-mips.h"
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#include "panic.h"
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#include "system.h"
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#include "kernel.h"
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#define NUM_DMA 6
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#define NUM_GPIO 128
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#define IRQ_MAX (IRQ_GPIO_0 + NUM_GPIO)
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static int irq;
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static void UIRQ(void)
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{
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panicf("Unhandled interrupt occurred: %d", irq);
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}
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#define intr(name) extern __attribute__((weak,alias("UIRQ"))) void name (void)
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intr(I2C);intr(EMC);intr(UHC);intr(UART0);intr(SADC);intr(MSC);intr(RTC);
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intr(SSI);intr(CIM);intr(AIC);intr(ETH);intr(TCU2);intr(TCU1);intr(TCU0);
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intr(UDC);intr(IPU);intr(LCD);
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intr(DMA0);intr(DMA1);intr(DMA2);intr(DMA3);intr(DMA4);intr(DMA5);
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intr(GPIO0);intr(GPIO1);intr(GPIO2);intr(GPIO3);intr(GPIO4);intr(GPIO5);
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intr(GPIO6);intr(GPIO7);intr(GPIO8);intr(GPIO9);intr(GPIO10);intr(GPIO11);
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intr(GPIO12);intr(GPIO13);intr(GPIO14);intr(GPIO15);intr(GPIO16);intr(GPIO17);
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intr(GPIO18);intr(GPIO19);intr(GPIO20);intr(GPIO21);intr(GPIO22);intr(GPIO23);
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intr(GPIO24);intr(GPIO25);intr(GPIO26);intr(GPIO27);intr(GPIO28);intr(GPIO29);
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intr(GPIO30);intr(GPIO31);intr(GPIO32);intr(GPIO33);intr(GPIO34);intr(GPIO35);
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intr(GPIO36);intr(GPIO37);intr(GPIO38);intr(GPIO39);intr(GPIO40);intr(GPIO41);
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intr(GPIO42);intr(GPIO43);intr(GPIO44);intr(GPIO45);intr(GPIO46);intr(GPIO47);
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intr(GPIO48);intr(GPIO49);intr(GPIO50);intr(GPIO51);intr(GPIO52);intr(GPIO53);
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intr(GPIO54);intr(GPIO55);intr(GPIO56);intr(GPIO57);intr(GPIO58);intr(GPIO59);
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intr(GPIO60);intr(GPIO61);intr(GPIO62);intr(GPIO63);intr(GPIO64);intr(GPIO65);
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intr(GPIO66);intr(GPIO67);intr(GPIO68);intr(GPIO69);intr(GPIO70);intr(GPIO71);
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intr(GPIO72);intr(GPIO73);intr(GPIO74);intr(GPIO75);intr(GPIO76);intr(GPIO77);
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intr(GPIO78);intr(GPIO79);intr(GPIO80);intr(GPIO81);intr(GPIO82);intr(GPIO83);
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intr(GPIO84);intr(GPIO85);intr(GPIO86);intr(GPIO87);intr(GPIO88);intr(GPIO89);
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intr(GPIO90);intr(GPIO91);intr(GPIO92);intr(GPIO93);intr(GPIO94);intr(GPIO95);
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intr(GPIO96);intr(GPIO97);intr(GPIO98);intr(GPIO99);intr(GPIO100);intr(GPIO101);
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intr(GPIO102);intr(GPIO103);intr(GPIO104);intr(GPIO105);intr(GPIO106);
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intr(GPIO107);intr(GPIO108);intr(GPIO109);intr(GPIO110);intr(GPIO111);
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intr(GPIO112);intr(GPIO113);intr(GPIO114);intr(GPIO115);intr(GPIO116);
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intr(GPIO117);intr(GPIO118);intr(GPIO119);intr(GPIO120);intr(GPIO121);
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intr(GPIO122);intr(GPIO123);intr(GPIO124);intr(GPIO125);intr(GPIO126);
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intr(GPIO127);
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static void (* const irqvector[])(void) =
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{
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I2C,EMC,UHC,UIRQ,UIRQ,UIRQ,UIRQ,UIRQ,
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UART0,UIRQ,UIRQ,SADC,UIRQ,MSC,RTC,SSI,
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CIM,AIC,ETH,UIRQ,TCU2,TCU1,TCU0,UDC,
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UIRQ,UIRQ,UIRQ,UIRQ,IPU,LCD,UIRQ,DMA0,
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DMA1,DMA2,DMA3,DMA4,DMA5,UIRQ,UIRQ,UIRQ,
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UIRQ,UIRQ,UIRQ,UIRQ,UIRQ,UIRQ,UIRQ,
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GPIO0,GPIO1,GPIO2,GPIO3,GPIO4,GPIO5,GPIO6,GPIO7,
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GPIO8,GPIO9,GPIO10,GPIO11,GPIO12,GPIO13,GPIO14,GPIO15,
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GPIO16,GPIO17,GPIO18,GPIO19,GPIO20,GPIO21,GPIO22,GPIO23,
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GPIO24,GPIO25,GPIO26,GPIO27,GPIO28,GPIO29,GPIO30,GPIO31,
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GPIO32,GPIO33,GPIO34,GPIO35,GPIO36,GPIO37,GPIO38,GPIO39,
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GPIO40,GPIO41,GPIO42,GPIO43,GPIO44,GPIO45,GPIO46,GPIO47,
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GPIO48,GPIO49,GPIO50,GPIO51,GPIO52,GPIO53,GPIO54,GPIO55,
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GPIO56,GPIO57,GPIO58,GPIO59,GPIO60,GPIO61,GPIO62,GPIO63,
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GPIO64,GPIO65,GPIO66,GPIO67,GPIO68,GPIO69,GPIO70,GPIO71,
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GPIO72,GPIO73,GPIO74,GPIO75,GPIO76,GPIO77,GPIO78,GPIO79,
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GPIO80,GPIO81,GPIO82,GPIO83,GPIO84,GPIO85,GPIO86,GPIO87,
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GPIO88,GPIO89,GPIO90,GPIO91,GPIO92,GPIO93,GPIO94,GPIO95,
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GPIO96,GPIO97,GPIO98,GPIO99,GPIO100,GPIO101,GPIO102,GPIO103,
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GPIO104,GPIO105,GPIO106,GPIO107,GPIO108,GPIO109,GPIO110,GPIO111,
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GPIO112,GPIO113,GPIO114,GPIO115,GPIO116,GPIO117,GPIO118,GPIO119,
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GPIO120,GPIO121,GPIO122,GPIO123,GPIO124,GPIO125,GPIO126,GPIO127
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};
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static unsigned int dma_irq_mask = 0;
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static unsigned int gpio_irq_mask[4] = {0};
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void system_enable_irq(unsigned int irq)
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{
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register unsigned int t;
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if ((irq >= IRQ_GPIO_0) && (irq <= IRQ_GPIO_0 + NUM_GPIO))
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{
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__gpio_unmask_irq(irq - IRQ_GPIO_0);
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t = (irq - IRQ_GPIO_0) >> 5;
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gpio_irq_mask[t] |= (1 << ((irq - IRQ_GPIO_0) & 0x1f));
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__intc_unmask_irq(IRQ_GPIO0 - t);
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}
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else if ((irq >= IRQ_DMA_0) && (irq <= IRQ_DMA_0 + NUM_DMA))
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{
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__dmac_channel_enable_irq(irq - IRQ_DMA_0);
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dma_irq_mask |= (1 << (irq - IRQ_DMA_0));
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__intc_unmask_irq(IRQ_DMAC);
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}
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else if (irq < 32)
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__intc_unmask_irq(irq);
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}
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static void dis_irq(unsigned int irq)
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{
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register unsigned int t;
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if ((irq >= IRQ_GPIO_0) && (irq <= IRQ_GPIO_0 + NUM_GPIO))
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{
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__gpio_mask_irq(irq - IRQ_GPIO_0);
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t = (irq - IRQ_GPIO_0) >> 5;
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gpio_irq_mask[t] &= ~(1 << ((irq - IRQ_GPIO_0) & 0x1f));
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if (!gpio_irq_mask[t])
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__intc_mask_irq(IRQ_GPIO0 - t);
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}
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else if ((irq >= IRQ_DMA_0) && (irq <= IRQ_DMA_0 + NUM_DMA))
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{
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__dmac_channel_disable_irq(irq - IRQ_DMA_0);
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dma_irq_mask &= ~(1 << (irq - IRQ_DMA_0));
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if (!dma_irq_mask)
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__intc_mask_irq(IRQ_DMAC);
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}
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else if (irq < 32)
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__intc_mask_irq(irq);
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}
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static void ack_irq(unsigned int irq)
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{
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if ((irq >= IRQ_GPIO_0) && (irq <= IRQ_GPIO_0 + NUM_GPIO))
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{
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__intc_ack_irq(IRQ_GPIO0 - ((irq - IRQ_GPIO_0)>>5));
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__gpio_ack_irq(irq - IRQ_GPIO_0);
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}
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else if ((irq >= IRQ_DMA_0) && (irq <= IRQ_DMA_0 + NUM_DMA))
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__intc_ack_irq(IRQ_DMAC);
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else if (irq < 32)
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__intc_ack_irq(irq);
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}
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static int get_irq_number(void)
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{
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static unsigned long ipl;
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register int irq;
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ipl |= REG_INTC_IPR;
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if (ipl == 0)
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return -1;
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for (irq = 31; irq >= 0; irq--)
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if (ipl & (1 << irq))
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break;
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if (irq < 0)
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return -1;
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ipl &= ~(1 << irq);
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switch (irq)
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{
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case IRQ_GPIO0:
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irq = __gpio_group_irq(0) + IRQ_GPIO_0;
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break;
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case IRQ_GPIO1:
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irq = __gpio_group_irq(1) + IRQ_GPIO_0 + 32;
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break;
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case IRQ_GPIO2:
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irq = __gpio_group_irq(2) + IRQ_GPIO_0 + 64;
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break;
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case IRQ_GPIO3:
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irq = __gpio_group_irq(3) + IRQ_GPIO_0 + 96;
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break;
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case IRQ_DMAC:
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irq = __dmac_get_irq() + IRQ_DMA_0;
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break;
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}
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return irq;
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}
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void intr_handler(void)
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{
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int irq = get_irq_number();
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if(UNLIKELY(irq < 0))
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return;
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ack_irq(irq);
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if(LIKELY(irq > 0))
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irqvector[irq-1]();
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}
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#define EXC(x,y) case (x): return (y);
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static char* parse_exception(unsigned int cause)
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{
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switch(cause & M_CauseExcCode)
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{
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EXC(EXC_INT, "Interrupt");
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EXC(EXC_MOD, "TLB Modified");
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EXC(EXC_TLBL, "TLB Exception (Load or Ifetch)");
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EXC(EXC_ADEL, "Address Error (Load or Ifetch)");
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EXC(EXC_ADES, "Address Error (Store)");
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EXC(EXC_TLBS, "TLB Exception (Store)");
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EXC(EXC_IBE, "Instruction Bus Error");
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EXC(EXC_DBE, "Data Bus Error");
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EXC(EXC_SYS, "Syscall");
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EXC(EXC_BP, "Breakpoint");
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EXC(EXC_RI, "Reserved Instruction");
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EXC(EXC_CPU, "Coprocessor Unusable");
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EXC(EXC_OV, "Overflow");
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EXC(EXC_TR, "Trap Instruction");
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EXC(EXC_FPE, "Floating Point Exception");
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EXC(EXC_C2E, "COP2 Exception");
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EXC(EXC_MDMX, "MDMX Exception");
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EXC(EXC_WATCH, "Watch Exception");
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EXC(EXC_MCHECK, "Machine Check Exception");
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EXC(EXC_CacheErr, "Cache error caused re-entry to Debug Mode");
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default:
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return NULL;
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}
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}
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void exception_handler(void* stack_ptr, unsigned int cause, unsigned int epc)
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{
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panicf("Exception occurred: %s [0x%08x] at 0x%08x (stack at 0x%08x)", parse_exception(cause), cause, epc, (unsigned int)stack_ptr);
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}
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void tlb_refill_handler(void)
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{
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panicf("TLB refill handler at 0x%08lx! [0x%x]", read_c0_epc(), read_c0_badvaddr());
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}
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void udelay(unsigned int usec)
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{
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unsigned int i = usec * (__cpm_get_cclk() / 2000000);
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__asm__ __volatile__ (
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".set noreorder \n"
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"1: \n"
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"bne %0, $0, 1b \n"
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"addi %0, %0, -1 \n"
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".set reorder \n"
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: "=r" (i)
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: "0" (i)
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);
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}
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void mdelay(unsigned int msec)
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{
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unsigned int i;
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for(i=0; i<msec; i++)
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udelay(1000);
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}
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static int dma_count = 0;
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void dma_enable(void)
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{
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if(++dma_count == 1)
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{
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__cpm_start_dmac();
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REG_DMAC_DCCSR(0) = 0;
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REG_DMAC_DCCSR(1) = 0;
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REG_DMAC_DCCSR(2) = 0;
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REG_DMAC_DCCSR(3) = 0;
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REG_DMAC_DCCSR(4) = 0;
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REG_DMAC_DCCSR(5) = 0;
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REG_DMAC_DMACR = (DMAC_DMACR_PR_012345 | DMAC_DMACR_DMAE);
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}
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}
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void dma_disable(void)
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{
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if(--dma_count == 0)
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{
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REG_DMAC_DMACR &= ~DMAC_DMACR_DMAE;
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__cpm_stop_dmac();
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}
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}
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/* PLL output clock = EXTAL * NF / (NR * NO)
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*
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* NF = FD + 2, NR = RD + 2
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* NO = 1 (if OD = 0), NO = 2 (if OD = 1 or 2), NO = 4 (if OD = 3)
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*/
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static void pll_init(void) ICODE_ATTR;
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static void pll_init(void)
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{
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register unsigned int cfcr, plcr1;
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int n2FR[33] = {
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0, 0, 1, 2, 3, 0, 4, 0, 5, 0, 0, 0, 6, 0, 0, 0,
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7, 0, 0, 0, 0, 0, 0, 0, 8, 0, 0, 0, 0, 0, 0, 0,
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9
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};
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int div[5] = {1, 3, 3, 3, 3}; /* divisors of I:S:P:L:M */
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int nf, pllout2;
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cfcr = CPM_CPCCR_CLKOEN |
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CPM_CPCCR_PCS |
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(n2FR[div[0]] << CPM_CPCCR_CDIV_BIT) |
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(n2FR[div[1]] << CPM_CPCCR_HDIV_BIT) |
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(n2FR[div[2]] << CPM_CPCCR_PDIV_BIT) |
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(n2FR[div[3]] << CPM_CPCCR_MDIV_BIT) |
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(n2FR[div[4]] << CPM_CPCCR_LDIV_BIT) |
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CPM_CPCCR_CE; /* Perform clock divisions immediately */
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pllout2 = (cfcr & CPM_CPCCR_PCS) ? CPU_FREQ : (CPU_FREQ / 2);
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/* Init USB Host clock, pllout2 must be n*48MHz */
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REG_CPM_UHCCDR = pllout2 / 48000000 - 1;
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nf = CPU_FREQ * 2 / CFG_EXTAL;
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plcr1 = ((nf - 2) << CPM_CPPCR_PLLM_BIT) | /* FD */
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(0 << CPM_CPPCR_PLLN_BIT) | /* RD=0, NR=2 */
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(0 << CPM_CPPCR_PLLOD_BIT) | /* OD=0, NO=1 */
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(0x20 << CPM_CPPCR_PLLST_BIT) | /* PLL stable time */
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CPM_CPPCR_PLLEN; /* enable PLL */
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/* init PLL */
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REG_CPM_CPCCR = cfcr;
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REG_CPM_CPPCR = plcr1;
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}
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// SDRAM paramters
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#define CFG_SDRAM_BW16 0 /* Data bus width: 0-32bit, 1-16bit */
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#define CFG_SDRAM_BANK4 1 /* Banks each chip: 0-2bank, 1-4bank */
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#define CFG_SDRAM_ROW 12 /* Row address: 11 to 13 */
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#define CFG_SDRAM_COL 8 /* Column address: 8 to 12 */
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#define CFG_SDRAM_CASL 2 /* CAS latency: 2 or 3 */
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// SDRAM Timings, unit: ns
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#define CFG_SDRAM_TRAS 45 /* RAS# Active Time */
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#define CFG_SDRAM_RCD 20 /* RAS# to CAS# Delay */
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#define CFG_SDRAM_TPC 20 /* RAS# Precharge Time */
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#define CFG_SDRAM_TRWL 7 /* Write Latency Time */
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#define CFG_SDRAM_TREF 7812 /* Refresh period: 8192 refresh cycles/64ms */
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/*
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* Init SDRAM memory.
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*/
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static void sdram_init(void) ICODE_ATTR;
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static void sdram_init(void)
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{
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register unsigned int dmcr0, dmcr, sdmode, tmp, cpu_clk, mem_clk, ns;
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unsigned int cas_latency_sdmr[2] = {
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EMC_SDMR_CAS_2,
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EMC_SDMR_CAS_3,
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};
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unsigned int cas_latency_dmcr[2] = {
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1 << EMC_DMCR_TCL_BIT, /* CAS latency is 2 */
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2 << EMC_DMCR_TCL_BIT /* CAS latency is 3 */
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};
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int div[] = { 1, 2, 3, 4, 6, 8, 12, 16, 24, 32 };
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cpu_clk = CPU_FREQ;
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mem_clk = cpu_clk * div[__cpm_get_cdiv()] / div[__cpm_get_mdiv()];
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//REG_EMC_BCR = 0; /* Disable bus release */
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REG_EMC_RTCSR = 0; /* Disable clock for counting */
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REG_EMC_RTCOR = 0;
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REG_EMC_RTCNT = 0;
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/* Fault DMCR value for mode register setting */
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#define SDRAM_ROW0 11
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#define SDRAM_COL0 8
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#define SDRAM_BANK40 0
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dmcr0 = ((SDRAM_ROW0 - 11) << EMC_DMCR_RA_BIT) |
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((SDRAM_COL0 - 8) << EMC_DMCR_CA_BIT) |
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(SDRAM_BANK40 << EMC_DMCR_BA_BIT) |
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(CFG_SDRAM_BW16 << EMC_DMCR_BW_BIT) |
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EMC_DMCR_EPIN | cas_latency_dmcr[((CFG_SDRAM_CASL == 3) ? 1 : 0)];
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/* Basic DMCR value */
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dmcr = ((CFG_SDRAM_ROW - 11) << EMC_DMCR_RA_BIT) |
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((CFG_SDRAM_COL - 8) << EMC_DMCR_CA_BIT) |
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(CFG_SDRAM_BANK4 << EMC_DMCR_BA_BIT) |
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(CFG_SDRAM_BW16 << EMC_DMCR_BW_BIT) |
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EMC_DMCR_EPIN | cas_latency_dmcr[((CFG_SDRAM_CASL == 3) ? 1 : 0)];
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/* SDRAM timimg */
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ns = 1000000000 / mem_clk;
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tmp = CFG_SDRAM_TRAS / ns;
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if (tmp < 4)
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tmp = 4;
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if (tmp > 11)
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tmp = 11;
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dmcr |= ((tmp - 4) << EMC_DMCR_TRAS_BIT);
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tmp = CFG_SDRAM_RCD / ns;
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if (tmp > 3)
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tmp = 3;
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dmcr |= (tmp << EMC_DMCR_RCD_BIT);
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tmp = CFG_SDRAM_TPC / ns;
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if (tmp > 7)
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tmp = 7;
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dmcr |= (tmp << EMC_DMCR_TPC_BIT);
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tmp = CFG_SDRAM_TRWL / ns;
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if (tmp > 3)
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tmp = 3;
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dmcr |= (tmp << EMC_DMCR_TRWL_BIT);
|
|
tmp = (CFG_SDRAM_TRAS + CFG_SDRAM_TPC) / ns;
|
|
if (tmp > 14)
|
|
tmp = 14;
|
|
dmcr |= (((tmp + 1) >> 1) << EMC_DMCR_TRC_BIT);
|
|
|
|
/* SDRAM mode value */
|
|
sdmode = EMC_SDMR_BT_SEQ |
|
|
EMC_SDMR_OM_NORMAL |
|
|
EMC_SDMR_BL_4 | cas_latency_sdmr[((CFG_SDRAM_CASL == 3) ? 1 : 0)];
|
|
|
|
/* Stage 1. Precharge all banks by writing SDMR with DMCR.MRSET=0 */
|
|
REG_EMC_DMCR = dmcr;
|
|
REG8(EMC_SDMR0 | sdmode) = 0;
|
|
|
|
/* Wait for precharge, > 200us */
|
|
tmp = (cpu_clk / 1000000) * 1000;
|
|
while (tmp--);
|
|
|
|
/* Stage 2. Enable auto-refresh */
|
|
REG_EMC_DMCR = dmcr | EMC_DMCR_RFSH;
|
|
|
|
tmp = CFG_SDRAM_TREF / ns;
|
|
tmp = tmp / 64 + 1;
|
|
if (tmp > 0xff)
|
|
tmp = 0xff;
|
|
REG_EMC_RTCOR = tmp;
|
|
REG_EMC_RTCNT = 0;
|
|
REG_EMC_RTCSR = EMC_RTCSR_CKS_64; /* Divisor is 64, CKO/64 */
|
|
|
|
/* Wait for number of auto-refresh cycles */
|
|
tmp = (cpu_clk / 1000000) * 1000;
|
|
while (tmp--);
|
|
|
|
/* Stage 3. Mode Register Set */
|
|
REG_EMC_DMCR = dmcr0 | EMC_DMCR_RFSH | EMC_DMCR_MRSET;
|
|
REG8(EMC_SDMR0 | sdmode) = 0;
|
|
|
|
/* Set back to basic DMCR value */
|
|
REG_EMC_DMCR = dmcr | EMC_DMCR_RFSH | EMC_DMCR_MRSET;
|
|
|
|
/* everything is ok now */
|
|
}
|
|
|
|
/* Gets called *before* main */
|
|
void ICODE_ATTR system_main(void)
|
|
{
|
|
int i;
|
|
|
|
__dcache_writeback_all();
|
|
__icache_invalidate_all();
|
|
|
|
write_c0_status(1 << 28 | 1 << 10 ); /* Enable CP | Mask interrupt 2 */
|
|
|
|
/* Disable all interrupts */
|
|
for(i=0; i<IRQ_MAX; i++)
|
|
dis_irq(i);
|
|
|
|
mmu_init();
|
|
pll_init();
|
|
sdram_init();
|
|
|
|
/* Disable unneeded clocks, clocks are enabled when needed */
|
|
__cpm_stop_all();
|
|
__cpm_suspend_usbhost();
|
|
|
|
/* Enable interrupts at core level */
|
|
enable_interrupt();
|
|
}
|
|
|
|
void system_reboot(void)
|
|
{
|
|
REG_WDT_TCSR = WDT_TCSR_PRESCALE4 | WDT_TCSR_EXT_EN;
|
|
REG_WDT_TCNT = 0;
|
|
REG_WDT_TDR = JZ_EXTAL/1000; /* reset after 4ms */
|
|
REG_TCU_TSCR = TCU_TSSR_WDTSC; /* enable wdt clock */
|
|
REG_WDT_TCER = WDT_TCER_TCEN; /* wdt start */
|
|
|
|
while (1);
|
|
}
|
|
|
|
void system_exception_wait(void)
|
|
{
|
|
/* check for power button without including any .h file */
|
|
while (1)
|
|
{
|
|
if( (~(*(volatile unsigned int *)(0xB0010300))) & (1 << 29) )
|
|
break;
|
|
}
|
|
}
|
|
|
|
void power_off(void)
|
|
{
|
|
/* Enable RTC clock */
|
|
__cpm_start_rtc();
|
|
|
|
/* Put system into hibernate mode */
|
|
__rtc_clear_alarm_flag();
|
|
__rtc_clear_hib_stat_all();
|
|
/* __rtc_set_scratch_pattern(0x12345678); */
|
|
__rtc_enable_alarm_wakeup();
|
|
__rtc_set_hrcr_val(0xFE0);
|
|
__rtc_set_hwfcr_val(0xFFFF << 4);
|
|
__rtc_power_down();
|
|
|
|
while(1);
|
|
}
|
|
|
|
void system_init(void)
|
|
{
|
|
}
|
|
|
|
int system_memory_guard(int newmode)
|
|
{
|
|
(void)newmode;
|
|
return 0;
|
|
}
|