416 lines
14 KiB
C
416 lines
14 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2021 Aidan MacDonald
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include "nand-x1000.h"
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#include "sfc-x1000.h"
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#include "system.h"
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#include <string.h>
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/* cmd mode a d phase format has data */
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#define NANDCMD_RESET SFC_CMD(0xff, SFC_TMODE_1_1_1, 0, 0, SFC_PFMT_ADDR_FIRST, 0)
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#define NANDCMD_READID(x,y) SFC_CMD(0x9f, SFC_TMODE_1_1_1, x, y, SFC_PFMT_ADDR_FIRST, 1)
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#define NANDCMD_WR_EN SFC_CMD(0x06, SFC_TMODE_1_1_1, 0, 0, SFC_PFMT_ADDR_FIRST, 0)
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#define NANDCMD_GET_FEATURE SFC_CMD(0x0f, SFC_TMODE_1_1_1, 1, 0, SFC_PFMT_ADDR_FIRST, 1)
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#define NANDCMD_SET_FEATURE SFC_CMD(0x1f, SFC_TMODE_1_1_1, 1, 0, SFC_PFMT_ADDR_FIRST, 1)
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#define NANDCMD_PAGE_READ(x) SFC_CMD(0x13, SFC_TMODE_1_1_1, x, 0, SFC_PFMT_ADDR_FIRST, 0)
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#define NANDCMD_READ_CACHE(x) SFC_CMD(0x0b, SFC_TMODE_1_1_1, x, 8, SFC_PFMT_ADDR_FIRST, 1)
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#define NANDCMD_READ_CACHE_x4(x) SFC_CMD(0x6b, SFC_TMODE_1_1_4, x, 8, SFC_PFMT_ADDR_FIRST, 1)
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#define NANDCMD_PROGRAM_LOAD(x) SFC_CMD(0x02, SFC_TMODE_1_1_1, x, 0, SFC_PFMT_ADDR_FIRST, 1)
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#define NANDCMD_PROGRAM_LOAD_x4(x) SFC_CMD(0x32, SFC_TMODE_1_1_4, x, 0, SFC_PFMT_ADDR_FIRST, 1)
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#define NANDCMD_PROGRAM_EXECUTE(x) SFC_CMD(0x10, SFC_TMODE_1_1_1, x, 0, SFC_PFMT_ADDR_FIRST, 0)
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#define NANDCMD_BLOCK_ERASE(x) SFC_CMD(0xd8, SFC_TMODE_1_1_1, x, 0, SFC_PFMT_ADDR_FIRST, 0)
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/* Feature registers are found in linux/mtd/spinand.h,
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* apparently these are pretty standardized */
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#define FREG_PROT 0xa0
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#define FREG_PROT_UNLOCK 0x00
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#define FREG_CFG 0xb0
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#define FREG_CFG_OTP_ENABLE (1 << 6)
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#define FREG_CFG_ECC_ENABLE (1 << 4)
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#define FREG_CFG_QUAD_ENABLE (1 << 0)
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#define FREG_STATUS 0xc0
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#define FREG_STATUS_BUSY (1 << 0)
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#define FREG_STATUS_EFAIL (1 << 2)
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#define FREG_STATUS_PFAIL (1 << 3)
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#define FREG_STATUS_ECC_MASK (3 << 4)
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#define FREG_STATUS_ECC_NO_FLIPS (0 << 4)
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#define FREG_STATUS_ECC_HAS_FLIPS (1 << 4)
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#define FREG_STATUS_ECC_UNCOR_ERR (2 << 4)
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const nand_chip supported_nand_chips[] = {
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#if defined(FIIO_M3K) || defined(SHANLING_Q1)
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{
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/* ATO25D1GA */
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.mf_id = 0x9b,
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.dev_id = 0x12,
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.row_cycles = 3,
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.col_cycles = 2,
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.log2_ppb = 6, /* 64 pages */
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.page_size = 2048,
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.oob_size = 64,
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.nr_blocks = 1024,
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.clock_freq = 150000000,
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.dev_conf = jz_orf(SFC_DEV_CONF,
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CE_DL(1), HOLD_DL(1), WP_DL(1),
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CPHA(0), CPOL(0),
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TSH(7), TSETUP(0), THOLD(0),
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STA_TYPE_V(1BYTE), CMD_TYPE_V(8BITS),
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SMP_DELAY(1)),
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.flags = NAND_CHIPFLAG_QUAD | NAND_CHIPFLAG_HAS_QE_BIT,
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},
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#else
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{ 0 },
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#endif
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};
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const size_t nr_supported_nand_chips =
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sizeof(supported_nand_chips) / sizeof(nand_chip);
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static nand_drv static_nand_drv;
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static uint8_t static_scratch_buf[NAND_DRV_SCRATCHSIZE] CACHEALIGN_ATTR;
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static uint8_t static_page_buf[NAND_DRV_MAXPAGESIZE] CACHEALIGN_ATTR;
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nand_drv* nand_init(void)
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{
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static bool inited = false;
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if(!inited) {
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mutex_init(&static_nand_drv.mutex);
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static_nand_drv.scratch_buf = static_scratch_buf;
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static_nand_drv.page_buf = static_page_buf;
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static_nand_drv.refcount = 0;
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}
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return &static_nand_drv;
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}
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static uint8_t nand_get_reg(nand_drv* drv, uint8_t reg)
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{
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sfc_exec(NANDCMD_GET_FEATURE, reg, drv->scratch_buf, 1|SFC_READ);
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return drv->scratch_buf[0];
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}
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static void nand_set_reg(nand_drv* drv, uint8_t reg, uint8_t val)
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{
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drv->scratch_buf[0] = val;
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sfc_exec(NANDCMD_SET_FEATURE, reg, drv->scratch_buf, 1|SFC_WRITE);
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}
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static void nand_upd_reg(nand_drv* drv, uint8_t reg, uint8_t msk, uint8_t val)
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{
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uint8_t x = nand_get_reg(drv, reg);
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x &= ~msk;
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x |= val;
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nand_set_reg(drv, reg, x);
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}
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static bool identify_chip(nand_drv* drv)
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{
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/* Read ID command has some variations; Linux handles these 3:
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* - no address or dummy bytes
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* - 1 byte address, no dummy byte
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* - no address byte, 1 byte dummy
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*
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* Right now there is only a need for the 2nd variation, as that is
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* the method used by the ATO25D1GA.
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*
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* Some chips also output more than 2 ID bytes.
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*/
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sfc_exec(NANDCMD_READID(1, 0), 0, drv->scratch_buf, 2|SFC_READ);
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drv->mf_id = drv->scratch_buf[0];
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drv->dev_id = drv->scratch_buf[1];
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for(size_t i = 0; i < nr_supported_nand_chips; ++i) {
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const nand_chip* chip = &supported_nand_chips[i];
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if(chip->mf_id == drv->mf_id && chip->dev_id == drv->dev_id) {
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drv->chip = chip;
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return true;
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}
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}
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return false;
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}
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static void setup_chip_data(nand_drv* drv)
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{
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drv->ppb = 1 << drv->chip->log2_ppb;
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drv->fpage_size = drv->chip->page_size + drv->chip->oob_size;
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}
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static void setup_chip_commands(nand_drv* drv)
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{
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/* Select commands appropriate for the chip */
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drv->cmd_page_read = NANDCMD_PAGE_READ(drv->chip->row_cycles);
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drv->cmd_program_execute = NANDCMD_PROGRAM_EXECUTE(drv->chip->row_cycles);
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drv->cmd_block_erase = NANDCMD_BLOCK_ERASE(drv->chip->row_cycles);
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if(drv->chip->flags & NAND_CHIPFLAG_QUAD) {
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drv->cmd_read_cache = NANDCMD_READ_CACHE_x4(drv->chip->col_cycles);
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drv->cmd_program_load = NANDCMD_PROGRAM_LOAD_x4(drv->chip->col_cycles);
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} else {
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drv->cmd_read_cache = NANDCMD_READ_CACHE(drv->chip->col_cycles);
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drv->cmd_program_load = NANDCMD_PROGRAM_LOAD(drv->chip->col_cycles);
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}
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}
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static void setup_chip_registers(nand_drv* drv)
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{
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/* Set chip registers to enter normal operation */
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if(drv->chip->flags & NAND_CHIPFLAG_HAS_QE_BIT) {
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bool en = (drv->chip->flags & NAND_CHIPFLAG_QUAD) != 0;
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nand_upd_reg(drv, FREG_CFG, FREG_CFG_QUAD_ENABLE,
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en ? FREG_CFG_QUAD_ENABLE : 0);
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}
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/* Clear OTP bit to access the main data array */
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nand_upd_reg(drv, FREG_CFG, FREG_CFG_OTP_ENABLE, 0);
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/* Clear write protection bits */
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nand_set_reg(drv, FREG_PROT, FREG_PROT_UNLOCK);
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}
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int nand_open(nand_drv* drv)
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{
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if(drv->refcount > 0)
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return NAND_SUCCESS;
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/* Initialize the controller */
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sfc_open();
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sfc_set_dev_conf(supported_nand_chips[0].dev_conf);
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sfc_set_clock(supported_nand_chips[0].clock_freq);
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/* Send the software reset command */
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sfc_exec(NANDCMD_RESET, 0, NULL, 0);
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mdelay(10);
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/* Chip identification and setup */
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if(!identify_chip(drv))
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return NAND_ERR_UNKNOWN_CHIP;
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setup_chip_data(drv);
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setup_chip_commands(drv);
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/* Set new SFC parameters */
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sfc_set_dev_conf(drv->chip->dev_conf);
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sfc_set_clock(drv->chip->clock_freq);
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/* Enter normal operating mode */
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setup_chip_registers(drv);
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drv->refcount++;
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return NAND_SUCCESS;
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}
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void nand_close(nand_drv* drv)
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{
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if(drv->refcount == 0)
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return;
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/* Let's reset the chip... the idea is to restore the registers
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* to whatever they should "normally" be */
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sfc_exec(NANDCMD_RESET, 0, NULL, 0);
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mdelay(10);
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sfc_close();
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drv->refcount--;
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}
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static uint8_t nand_wait_busy(nand_drv* drv)
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{
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uint8_t reg;
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do {
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reg = nand_get_reg(drv, FREG_STATUS);
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} while(reg & FREG_STATUS_BUSY);
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return reg;
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}
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int nand_block_erase(nand_drv* drv, nand_block_t block)
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{
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sfc_exec(NANDCMD_WR_EN, 0, NULL, 0);
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sfc_exec(drv->cmd_block_erase, block, NULL, 0);
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uint8_t status = nand_wait_busy(drv);
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if(status & FREG_STATUS_EFAIL)
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return NAND_ERR_ERASE_FAIL;
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else
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return NAND_SUCCESS;
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}
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int nand_page_program(nand_drv* drv, nand_page_t page, const void* buffer)
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{
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sfc_exec(NANDCMD_WR_EN, 0, NULL, 0);
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sfc_exec(drv->cmd_program_load, 0, (void*)buffer, drv->fpage_size|SFC_WRITE);
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sfc_exec(drv->cmd_program_execute, page, NULL, 0);
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uint8_t status = nand_wait_busy(drv);
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if(status & FREG_STATUS_PFAIL)
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return NAND_ERR_PROGRAM_FAIL;
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else
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return NAND_SUCCESS;
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}
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int nand_page_read(nand_drv* drv, nand_page_t page, void* buffer)
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{
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sfc_exec(drv->cmd_page_read, page, NULL, 0);
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nand_wait_busy(drv);
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sfc_exec(drv->cmd_read_cache, 0, buffer, drv->fpage_size|SFC_READ);
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return NAND_SUCCESS;
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}
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int nand_read_bytes(nand_drv* drv, uint32_t byte_addr, uint32_t byte_len, void* buffer)
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{
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if(byte_len == 0)
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return NAND_SUCCESS;
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int rc;
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unsigned pg_size = drv->chip->page_size;
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nand_page_t page = byte_addr / pg_size;
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unsigned offset = byte_addr % pg_size;
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while(1) {
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rc = nand_page_read(drv, page, drv->page_buf);
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if(rc < 0)
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return rc;
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memcpy(buffer, &drv->page_buf[offset], MIN(pg_size, byte_len));
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if(byte_len <= pg_size)
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break;
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offset = 0;
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byte_len -= pg_size;
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buffer += pg_size;
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page++;
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}
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return NAND_SUCCESS;
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}
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int nand_write_bytes(nand_drv* drv, uint32_t byte_addr, uint32_t byte_len, const void* buffer)
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{
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if(byte_len == 0)
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return NAND_SUCCESS;
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int rc;
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unsigned pg_size = drv->chip->page_size;
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unsigned blk_size = pg_size << drv->chip->log2_ppb;
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if(byte_addr % blk_size != 0)
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return NAND_ERR_UNALIGNED;
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if(byte_len % blk_size != 0)
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return NAND_ERR_UNALIGNED;
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nand_page_t page = byte_addr / pg_size;
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nand_page_t end_page = page + (byte_len / pg_size);
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for(nand_block_t blk = page; blk < end_page; blk += drv->ppb) {
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rc = nand_block_erase(drv, blk);
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if(rc < 0)
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return rc;
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}
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for(; page != end_page; ++page) {
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memcpy(drv->page_buf, buffer, pg_size);
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memset(&drv->page_buf[pg_size], 0xff, drv->chip->oob_size);
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buffer += pg_size;
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rc = nand_page_program(drv, page, drv->page_buf);
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if(rc < 0)
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return rc;
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}
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return NAND_SUCCESS;
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}
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/* TODO - NAND driver future improvements
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*
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* 1. Support sofware or on-die ECC transparently. Support debug ECC bypass.
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*
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* It's probably best to add an API call to turn ECC on or off. Software
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* ECC and most or all on-die ECC implementations require some OOB bytes
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* to function; which leads us to the next problem...
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*
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* 2. Allow safe access to OOB areas
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*
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* The OOB data area is not fully available to users; it is also occupied
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* by ECC data and bad block markings. The NAND driver needs to provide a
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* mapping which allows OOB data users to map around those reserved areas,
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* otherwise it's not really possible to use OOB data.
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*
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* 3. Support partial page programming.
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*
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* This might already work. My understanding of NAND flash is that bits are
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* represented by charge deposited on flash cells. In the case of SLC flash,
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* cells are one bit. For MLC flash, cells can store more than one bit; but
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* MLC flash is much less reliable than SLC. We probably don't have to be
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* concerned about MLC flash, and its does not support partial programming
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* anyway due to the cell characteristics, so I will only consider SLC here.
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*
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* For SLC there are two cell states -- an uncharged cell represents a "1"
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* and a charged cell represents "0". Programming can only deposit charge
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* on a cell and erasing can only remove charge. Therefore, "programming" a
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* cell to 1 is actually a no-op.
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*
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* So, there's no datasheet which spells this out, but I suspect you just
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* set the areas you're not interested in programming to 0xff. Programming
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* can never change a written 0 back to a 1, so programming a 1 bit works
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* more like a "don't care" (= keep whatever value is already there).
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*
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* What _is_ given by the datasheets is limits on how many times you can
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* reprogram the same page without erasing it. This is an overall limit
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* called NOP (number of programs) in many datasheets. In addition to this,
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* sub-regions of the page have further limits: it's common for a 2048+64
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* byte page to be split into 8 regions, with four 512-byte main areas and
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* four 16-byte OOB areas. Usually, each subregion can only be programmed
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* once. However, you can write multiple subregions with a single program.
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*
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* Violating programming constraints could cause data loss, so we need to
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* communicate to upper layers what the limitations are here if they want
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* to use partial programming safely.
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*
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* Programming the same page more than once increases the overall stress
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* on the flash cells and can cause bitflips. For this reason, it's best
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* to keep the number of programs as low as possible. Some sources suggest
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* that programming the pages in a block in linear order is also better to
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* reduce stress, although I don't know why this would be.
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*
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* These program/read stresses can flip bits, but it's only due to residual
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* charge building up on uncharged cells; cells are not permanently damaged
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* by these kind of stresses. Erasing the block will remove the charge and
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* restore all the cells to a clean state.
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*
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* These slides are fairly informative on this subject:
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* - https://cushychicken.github.io/assets/cooke_inconvenient_truths.pdf
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*
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* 4. Bad block management
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*
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* This probably doesn't belong in the NAND layer but it seems wise to keep
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* at least a bad block table at the level of the NAND driver. Factory bad
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* block marks are usually some non-0xFF byte in the OOB area, but bad blocks
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* which develop over the device lifetime usually won't be marked; after all
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* they are unreliable, so we can't program a marking on them and expect it
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* to stick. So, most FTL systems keep a bad block table somewhere in flash
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* and update it whenever a block goes bad.
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*
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* So, in addition to a bad block marker scan, we should try to gather bad
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* block information from such tables.
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*/
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