291 lines
11 KiB
C
291 lines
11 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2014 Michael Sparmann
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* Copyright (C) 2014 by Marcin Bukat
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* Copyright (C) 2016 by Cástor Muñoz
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#ifndef __USB_DESIGNWARE_H__
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#define __USB_DESIGNWARE_H__
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#include <inttypes.h>
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#include "config.h"
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#ifndef REG32_PTR_T
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#define REG32_PTR_T volatile uint32_t *
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#endif
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/* Global registers */
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#define DWC_GOTGCTL (*((REG32_PTR_T)(OTGBASE + 0x00)))
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#define DWC_GOTGINT (*((REG32_PTR_T)(OTGBASE + 0x04)))
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#define DWC_GAHBCFG (*((REG32_PTR_T)(OTGBASE + 0x08)))
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#define PTXFELVL (1<<8)
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#define TXFELVL (1<<7)
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#define DMAEN (1<<5)
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#define HBSTLEN(x) ((x)<<1)
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#define HBSTLEN_SINGLE 0
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#define HBSTLEN_INCR 1
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#define HBSTLEN_INCR4 3
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#define HBSTLEN_INCR8 5
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#define HBSTLEN_INCR16 7
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#define GINT (1<<0)
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#define DWC_GUSBCFG (*((REG32_PTR_T)(OTGBASE + 0x0c)))
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#define FDMOD (1<<30)
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#define TRDT(x) ((x)<<10)
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#define DDRSEL (1<<7)
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#define PHSEL (1<<6)
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#define FSINTF (1<<5)
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#define ULPI_UTMI_SEL (1<<4)
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#define PHYIF16 (1<<3)
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#define DWC_GRSTCTL (*((REG32_PTR_T)(OTGBASE + 0x10)))
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#define AHBIDL (1<<31)
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#define TXFNUM(x) ((x)<<6)
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#define TXFFLSH (1<<5)
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#define RXFFLSH (1<<4)
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#define CSRST (1<<0)
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#define DWC_GINTSTS (*((REG32_PTR_T)(OTGBASE + 0x14)))
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#define WKUINT (1<<31)
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#define SRQINT (1<<30)
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#define DISCINT (1<<29)
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#define CIDSCHG (1<<28)
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#define PTXFE (1<<26)
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#define HCINT (1<<25)
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#define HPRTINT (1<<24)
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#define FETSUSP (1<<22)
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#define IPXFR (1<<21)
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#define IISOIXFR (1<<20)
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#define OEPINT (1<<19)
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#define IEPINT (1<<18)
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#define EPMIS (1<<17)
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#define EOPF (1<<15)
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#define ISOODPR (1<<14)
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#define ENUMDNE (1<<13)
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#define USBRST (1<<12)
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#define USBSUSP (1<<11)
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#define ESUSP (1<<10)
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#define GOUTNAKEFF (1<<7)
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#define GINAKEFF (1<<6)
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#define NPTXFE (1<<5)
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#define RXFLVL (1<<4)
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#define SOF (1<<3)
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#define OTGINT (1<<2)
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#define MMIS (1<<1)
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#define CMOD (1<<0)
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#define DWC_GINTMSK (*((REG32_PTR_T)(OTGBASE + 0x18)))
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#define DWC_GRXSTSR (*((REG32_PTR_T)(OTGBASE + 0x1c)))
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#define DWC_GRXSTSP (*((REG32_PTR_T)(OTGBASE + 0x20)))
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#define PKTSTS_GLOBALOUTNAK 1
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#define PKTSTS_OUTRX 2
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#define PKTSTS_HCHIN 2
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#define PKTSTS_OUTDONE 3
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#define PKTSTS_HCHIN_XFER_COMP 3
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#define PKTSTS_SETUPDONE 4
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#define PKTSTS_DATATOGGLEERR 5
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#define PKTSTS_SETUPRX 6
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#define PKTSTS_HCHHALTED 7
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#define DWC_GRXFSIZ (*((REG32_PTR_T)(OTGBASE + 0x24)))
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#ifdef USB_DW_SHARED_FIFO
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#define DWC_GNPTXFSIZ (*((REG32_PTR_T)(OTGBASE + 0x28)))
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#else
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#define DWC_TX0FSIZ (*((REG32_PTR_T)(OTGBASE + 0x28)))
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#endif
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#define DWC_GNPTXSTS (*((REG32_PTR_T)(OTGBASE + 0x2c)))
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#define DWC_GI2CCTL (*((REG32_PTR_T)(OTGBASE + 0x30)))
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/* reserved */
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#define DWC_GCCFG (*((REG32_PTR_T)(OTGBASE + 0x38)))
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#define NOVBUSSENS (1<<21)
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#define SOFOUTEN (1<<20)
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#define VBUSBSEN (1<<19)
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#define VBUSASEN (1<<18)
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#define I2CPADEN (1<<17)
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#define PWRDWN (1<<16)
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#define DWC_CID (*((REG32_PTR_T)(OTGBASE + 0x3c)))
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#define DWC_GSNPSID (*((REG32_PTR_T)(OTGBASE + 0x40)))
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#define DWC_GHWCFG1 (*((REG32_PTR_T)(OTGBASE + 0x44)))
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#define DWC_GHWCFG2 (*((REG32_PTR_T)(OTGBASE + 0x48)))
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#define DWC_GHWCFG3 (*((REG32_PTR_T)(OTGBASE + 0x4c)))
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#define DWC_GHWCFG4 (*((REG32_PTR_T)(OTGBASE + 0x50)))
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#define DWC_GLPMCFG (*((REG32_PTR_T)(OTGBASE + 0x54)))
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#define DWC_HPTXFSIZ (*((REG32_PTR_T)(OTGBASE + 0x100)))
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#define DWC_DIEPTXF(x) (*((REG32_PTR_T)(OTGBASE + 0x104 + 4*(x)))) /*0..15*/
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/* Host mode registers */
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#define DWC_HCFG (*((REG32_PTR_T)(OTGBASE + 0x400)))
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#define DWC_HFIR (*((REG32_PTR_T)(OTGBASE + 0x404)))
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#define DWC_HFNUM (*((REG32_PTR_T)(OTGBASE + 0x408)))
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/* reserved */
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#define DWC_HPTXSTS (*((REG32_PTR_T)(OTGBASE + 0x410)))
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#define DWC_HAINT (*((REG32_PTR_T)(OTGBASE + 0x414)))
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#define DWC_HAINTMSK (*((REG32_PTR_T)(OTGBASE + 0x418)))
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#define DWC_HPRT (*((REG32_PTR_T)(OTGBASE + 0x440)))
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#define DWC_HCCHAR(x) (*((REG32_PTR_T)(OTGBASE + 0x500 + 0x20*(x))))
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#define DWC_HCSPLT(x) (*((REG32_PTR_T)(OTGBASE + 0x504 + 0x20*(x))))
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#define DWC_HCINT(x) (*((REG32_PTR_T)(OTGBASE + 0x508 + 0x20*(x))))
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#define DWC_HCINTMSK(x) (*((REG32_PTR_T)(OTGBASE + 0x50c + 0x20*(x))))
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#define DWC_HCTSIZ(x) (*((REG32_PTR_T)(OTGBASE + 0x510 + 0x20*(x))))
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#define DWC_HCDMA(x) (*((REG32_PTR_T)(OTGBASE + 0x514 + 0x20*(x))))
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/* Device mode registers */
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#define DWC_DCFG (*((REG32_PTR_T)(OTGBASE + 0x800)))
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#define EPMISCNT(x) ((x)<<18)
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#define DAD(x) ((x)<<4)
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#define NZLSOHSK (1<<2)
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#define DWC_DCTL (*((REG32_PTR_T)(OTGBASE + 0x804)))
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#define POPRGDNE (1<<11)
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#define CGONAK (1<<10)
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#define SGONAK (1<<9)
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#define CGINAK (1<<8)
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#define SGINAK (1<<7)
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#define TCTL(x) ((x)<<4)
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#define GONSTS (1<<3)
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#define GINSTS (1<<2)
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#define SDIS (1<<1)
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#define RWUSIG (1<<0)
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#define DWC_DSTS (*((REG32_PTR_T)(OTGBASE + 0x808)))
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/* reserved */
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#define DWC_DIEPMSK (*((REG32_PTR_T)(OTGBASE + 0x810)))
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#define DWC_DOEPMSK (*((REG32_PTR_T)(OTGBASE + 0x814)))
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#define DWC_DAINT (*((REG32_PTR_T)(OTGBASE + 0x818)))
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#define DWC_DAINTMSK (*((REG32_PTR_T)(OTGBASE + 0x81c)))
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/* reserved */
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#define DWC_DVBUSDIS (*((REG32_PTR_T)(OTGBASE + 0x828)))
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#define DWC_DVBUSPULSE (*((REG32_PTR_T)(OTGBASE + 0x82c)))
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#ifdef USB_DW_SHARED_FIFO
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#define DWC_DTKNQR1 (*((REG32_PTR_T)(OTGBASE + 0x820)))
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#define DWC_DTKNQR2 (*((REG32_PTR_T)(OTGBASE + 0x824)))
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#define DWC_DTKNQR3 (*((REG32_PTR_T)(OTGBASE + 0x830)))
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#define DWC_DTKNQR4 (*((REG32_PTR_T)(OTGBASE + 0x834)))
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#else /* !USB_DW_SHARED_FIFO */
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#define DWC_DTHRCTL (*((REG32_PTR_T)(OTGBASE + 0x830)))
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#define ARPEN (1<<27)
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#define RXTHRLEN(x) ((x)<<17)
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#define RXTHREN (1<<16)
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#define TXTHRLEN(x) ((x)<<2)
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#define ISOTHREN (1<<1)
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#define NONISOTHREN (1<<0)
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#define DWC_DIEPEMPMSK (*((REG32_PTR_T)(OTGBASE + 0x834)))
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#define DWC_DEACHINT (*((REG32_PTR_T)(OTGBASE + 0x838)))
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#define DWC_DEACHINTMSK (*((REG32_PTR_T)(OTGBASE + 0x83c)))
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#define DWC_DIEPEACHMSK(x) (*((REG32_PTR_T)(OTGBASE + 0x840 + 4*(x))))
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#define DWC_DOEPEACHMSK(x) (*((REG32_PTR_T)(OTGBASE + 0x880 + 4*(x))))
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#endif
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#define DWC_DIEPCTL(x) (*((REG32_PTR_T)(OTGBASE + 0x900 + 0x20*(x))))
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#define DWC_DOEPCTL(x) (*((REG32_PTR_T)(OTGBASE + 0xb00 + 0x20*(x))))
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#define EPENA (1<<31)
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#define EPDIS (1<<30)
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#define SD0PID (1<<28)
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#define SNAK (1<<27)
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#define CNAK (1<<26)
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#define DTXFNUM(x) ((x)<<22)
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#define STALL (1<<21)
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#define EPTYP(x) ((x)<<18)
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#define EPTYP_CONTROL 0
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#define EPTYP_ISOCHRONOUS 1
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#define EPTYP_BULK 2
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#define EPTYP_INTERRUPT 3
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#define NAKSTS (1<<17)
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#define USBAEP (1<<15)
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#define NEXTEP(x) ((x)<<11)
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#define DWC_DIEPINT(x) (*((REG32_PTR_T)(OTGBASE + 0x908 + 0x20*(x))))
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#define DWC_DOEPINT(x) (*((REG32_PTR_T)(OTGBASE + 0xb08 + 0x20*(x))))
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#define SETUPRECVD (1<<15) /* control OUT */
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#define TXFE (1<<7) /* IN */
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#define BACK2BACKSETUP (1<<6) /* control OUT */
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#define INEPNE (1<<6) /* IN */
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#define STATUSRECVD (1<<5) /* control OUT */
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#define ITEPMIS (1<<5) /* IN */
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#define ITTXFE (1<<4) /* IN */
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#define OTEPDIS (1<<4) /* OUT */
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#define TOC (1<<3) /* control IN */
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#define STUP (1<<3) /* control OUT */
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#define AHBERR (1<<2)
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#define EPDISD (1<<1)
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#define XFRC (1<<0)
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#define DWC_DIEPTSIZ(x) (*((REG32_PTR_T)(OTGBASE + 0x910 + 0x20*(x))))
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#define DWC_DOEPTSIZ(x) (*((REG32_PTR_T)(OTGBASE + 0xb10 + 0x20*(x))))
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#define MCCNT(x) ((x)<<29) /* IN */
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#define STUPCNT(x) ((x)<<29) /* control OUT */
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#define RXDPID(x) ((x)<<29) /* isochronous OUT */
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#define PKTCNT(x) ((x)<<19)
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#define XFERSIZE(x) ((x)<<0)
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#define DWC_DIEPDMA(x) (*((REG32_PTR_T)(OTGBASE + 0x914 + 0x20*(x))))
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#define DWC_DOEPDMA(x) (*((REG32_PTR_T)(OTGBASE + 0xb14 + 0x20*(x))))
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#define DWC_DTXFSTS(x) (*((REG32_PTR_T)(OTGBASE + 0x918 + 0x20*(x))))
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#define DWC_PCGCCTL (*((REG32_PTR_T)(OTGBASE + 0xe00)))
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#define DWC_DFIFO(x) (*((REG32_PTR_T)(OTGBASE + 0x1000 + 0x1000*(x))))
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/* Device mode registers by (epnum,epdir), d==0 -> IN */
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#define DWC_EPCTL(n,d) (*((REG32_PTR_T)(OTGBASE + 0x900 + 0x200*(d) + 0x20*(n))))
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#define DWC_EPINT(n,d) (*((REG32_PTR_T)(OTGBASE + 0x908 + 0x200*(d) + 0x20*(n))))
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#define DWC_EPTSIZ(n,d) (*((REG32_PTR_T)(OTGBASE + 0x910 + 0x200*(d) + 0x20*(n))))
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#define DWC_EPDMA(n,d) (*((REG32_PTR_T)(OTGBASE + 0x914 + 0x200*(d) + 0x20*(n))))
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/* HS PHY/interface configuration */
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#define DWC_PHYTYPE_UTMI_8 (0)
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#define DWC_PHYTYPE_UTMI_16 (PHYIF16)
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#define DWC_PHYTYPE_ULPI_SDR (ULPI_UTMI_SEL)
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#define DWC_PHYTYPE_ULPI_DDR (ULPI_UTMI_SEL|DDRSEL)
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/* configure USB OTG capabilities on SoC */
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struct usb_dw_config
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{
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uint8_t phytype; /* DWC_PHYTYPE_ */
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uint16_t rx_fifosz;
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uint16_t nptx_fifosz;
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uint16_t ptx_fifosz;
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#ifdef USB_DW_SHARED_FIFO
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bool use_ptxfifo_as_plain_buffer;
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#endif
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#ifdef USB_DW_ARCH_SLAVE
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bool disable_double_buffering;
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#else
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uint8_t ahb_burst_len; /* HBSTLEN_ */
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#ifndef USB_DW_SHARED_FIFO
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uint8_t ahb_threshold;
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#endif
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#endif
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};
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extern const struct usb_dw_config usb_dw_config;
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extern void usb_dw_target_enable_clocks(void);
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extern void usb_dw_target_disable_clocks(void);
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extern void usb_dw_target_enable_irq(void);
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extern void usb_dw_target_disable_irq(void);
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extern void usb_dw_target_clear_irq(void);
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#endif /* __USB_DESIGNWARE_H__ */
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