536 lines
14 KiB
ArmAsm
536 lines
14 KiB
ArmAsm
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id: crt0.S 18776 2008-10-11 18:32:17Z gevaerts $
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*
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* Copyright (C) 2008 by Marcoen Hirschberg
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* Copyright (C) 2008 by Denes Balatoni
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include "config.h"
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#include "cpu.h"
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/* Meizu M3 SDRAM settings */
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#ifdef MEIZU_M3
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#define SDR_DSS_SEL_B 1
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#define SDR_DSS_SEL_O 1
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#define SDR_DSS_SEL_C 1
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#define SDR_TIMING 0x6A491D
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#define SDR_CONFIG 0x900
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#define SDR_MRS 0x37
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#define SDR_EMRS 0x4000
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#endif
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/* Meizu M6SP SDRAM settings */
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#ifdef MEIZU_M6SP
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#define SDR_DSS_SEL_B 5
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#define SDR_DSS_SEL_O 2
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#define SDR_DSS_SEL_C 2
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#define SDR_TIMING 0x6A4965
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#define SDR_CONFIG 0x700
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#define SDR_MRS 0x33
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#define SDR_EMRS 0x4033
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#endif
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.section .intvect,"ax",%progbits
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.global start
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.global _newstart
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/* Exception vectors */
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start:
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b _newstart
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ldr pc, =undef_instr_handler
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ldr pc, =software_int_handler
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ldr pc, =prefetch_abort_handler
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ldr pc, =data_abort_handler
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ldr pc, =reserved_handler
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ldr pc, =irq_handler
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ldr pc, =fiq_handler
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#if CONFIG_CPU==S5L8700
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.word 0x43554644 /* DFUC */
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#endif
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.ltorg
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_newstart:
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#if CONFIG_CPU!=S5L8701 || !defined(BOOTLOADER)
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ldr pc, =newstart2 // we do not want to execute from 0x0 as iram will be mapped there
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.section .init.text,"ax",%progbits
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newstart2:
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#endif
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msr cpsr_c, #0xd3 /* enter supervisor mode, disable IRQ/FIQ */
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#ifdef ROCKBOX_BIG_ENDIAN
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mov r1, #0x80
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mrc 15, 0, r0, c1, c0, 0
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orr r0, r0, r1
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mcr 15, 0, r0, c1, c0, 0 // set bigendian
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#endif
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ldr r1, =0x3c800000 // disable watchdog
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mov r0, #0xa5
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str r0, [r1]
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mov r0, #0
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mov r1, #0x39c00000
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str r0, [r1,#0x08] // mask all interrupts
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str r0, [r1,#0x20] // mask all external interrupts
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mvn r0, #0
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str r0, [r1,#0x1c] // clear pending external interrupts
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str r0, [r1] // irq priority
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str r0, [r1,#0x10] // clear pending interrupts
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// ldr r1, =0x3cf00000
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// ldr r0, [r1]
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// mvn r2, #0x30
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// and r0, r0, r2
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// mov r2, #0x10
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// orr r0, r0, r2
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// str r0, [r1]
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// ldr r0, [r1,#0x04]
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// mov r2, #4
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// orr r0, r0, r2
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// str r0, [r1,#0x04] // switch backlight on
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#if CONFIG_CPU==S5L8701
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ldr r1, =0x38200000
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ldr r2, [r1]
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orr r2, r2, #1
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bic r2, r2, #0x10000
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str r2, [r1] // remap iram to address 0x0
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#ifdef BOOTLOADER
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/* Relocate ourself to IRAM - we have been loaded to DRAM */
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mov r0, #0x08000000 /* source (DRAM) */
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mov r1, #0x22000000 /* dest (IRAM) */
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ldr r2, =_dataend
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1:
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cmp r2, r1
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ldrhi r3, [r0], #4
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strhi r3, [r1], #4
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bhi 1b
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ldr pc, =start_loc /* jump to the relocated start_loc: */
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start_loc:
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#endif /* BOOTLOADER */
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#endif /* CONFIG_CPU==S5L8701 */
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#if !(CONFIG_CPU==S5L8701 && defined(BOOTLOADER))
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ldr r1, =0x3c500000
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ldr r0, =0x00800080
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str r0, [r1] // CLKCON
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mov r0, #0
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str r0, [r1,#0x24] // PLLCON
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#ifdef IPOD_NANO2G
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ldr r0, =0x021200 // pdiv=2, mdiv=0x12 sdiv=0, 192 MHz
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#else
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ldr r0, =0x1ad200 // pdiv=0x1a, mdiv=0xd2 sdiv=0
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#endif
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str r0, [r1,#0x04] // PLL0PMS
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mov r0, #0
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str r0, [r1,#0x08] // PLL1PMS
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ldr r0, =280
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str r0, [r1,#0x14] // PLL0LCNT
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mov r0, #3
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str r0, [r1,#0x24] // PLLCON
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1:
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ldr r0, [r1,#0x20] // PLLLOCK
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tst r0, #1
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beq 1b
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mov r0, #0x280
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str r0, [r1,#0x3c] // CLKCON2
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ldr r0, =0x20803180 // FCLK_CPU = 200MHz, HCLK = 100MHz, PCLK = 50MHz, other clocks off
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str r0, [r1] // CLKCON
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mov r0, #0x37 // SCLK = 25MHz
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str r0, [r1,#0x10] // CLKCON3
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ldr r2, =0xc0000078
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mrc 15, 0, r0, c1, c0, 0
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mvn r1, #0xc0000000
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and r0, r0, r1
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orr r0, r0, r2
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mcr 15, 0, r0, c1, c0, 0 // asynchronous clocking mode
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nop
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nop
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nop
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nop
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#endif
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// ldr r0, =0x10100000
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// ldr r1, =0x38200034
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// str r0, [r1] // SRAM0/1 data width 16 bit
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// ldr r0, =0x00220922
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// ldr r7, =0x38200038
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// str r0, [r7] // SRAM0/1 clocks
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// ldr r0, =0x00220922
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// ldr r9, =0x3820003c
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// str r0, [r9] // SRAM2/3 clocks
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// nop
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// nop
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// nop
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// nop
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/* The following two sections of code (i.e. Nano2G and Meizus) should
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be unified at some point. */
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#ifdef IPOD_NANO2G
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ldr r1, =0x3c500000
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ldr r0, =0xffdff7ff
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str r0, [r1,#0x28] // PWRCON
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ldr r0, =0xffffef7e
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str r0, [r1,#0x40] // PWRCONEXT
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mrc 15, 0, r0, c1, c0, 0
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bic r0, r0, #0x1000
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bic r0, r0, #0x5
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mcr 15, 0, r0, c1, c0, 0 // disable caches and protection unit
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mov r1, #0
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1:
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mov r0, #0
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2:
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orr r2, r1, r0
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mcr 15, 0, r2, c7, c14, 2 // clean and flush dcache single entry
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add r0, r0, #0x10
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cmp r0, #0x40
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bne 2b
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add r1, r1, #0x4000000
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cmp r1, #0x0
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bne 1b
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nop
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nop
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mov r0, #0
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mcr 15, 0, r0, c7, c10, 4 // clean and flush whole dcache
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mcr 15, 0, r0, c7, c5, 0 // flush icache
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mcr 15, 0, r0, c7, c6, 0 // flush dcache
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mov r0, #0x3f
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mcr 15, 0, r0, c6, c0, 1 // CS0: 4GB at offset 0 - everything
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mcr 15, 0, r0, c6, c0, 0 // DS0: 4GB at offset 0 - everything
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#ifdef IPOD_NANO2G
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mov r0, #0x31 // FIXME: calculate that from MEMORYSIZE
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#else
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mov r0, #0x2f // FIXME: calculate that from MEMORYSIZE
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#endif
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mcr 15, 0, r0, c6, c1, 1 // CS1: SRAM/SDRAM mirror
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mcr 15, 0, r0, c6, c1, 0 // DS1: SRAM/SDRAM mirror
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add r0, r0, #0x08000000
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mcr 15, 0, r0, c6, c2, 1 // CS2: SDRAM
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mcr 15, 0, r0, c6, c2, 0 // DS2: SDRAM
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ldr r0, =0x22000023
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mcr 15, 0, r0, c6, c3, 1 // CS3: SRAM
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mcr 15, 0, r0, c6, c3, 0 // DS3: SRAM
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ldr r0, =0x24000027
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mcr 15, 0, r0, c6, c4, 1 // CS4: NOR flash
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mcr 15, 0, r0, c6, c4, 0 // DS4: NOR flash
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mov r0, #0
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mcr 15, 0, r0, c6, c5, 1 // CS5: unused
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mcr 15, 0, r0, c6, c5, 0 // DS5: unused
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mcr 15, 0, r0, c6, c6, 1 // CS6: unused
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mcr 15, 0, r0, c6, c6, 0 // DS6: unused
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mcr 15, 0, r0, c6, c7, 1 // CS7: unused
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mcr 15, 0, r0, c6, c7, 0 // DS7: unused
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mov r0, #0x1e
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mcr 15, 0, r0, c2, c0, 1 // CS1-4: cacheable
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mcr 15, 0, r0, c2, c0, 0 // DS1-4: cacheable
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mcr 15, 0, r0, c3, c0, 0 // DS1-4: write cacheable
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ldr r0, =0x000003ff
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mcr 15, 0, r0, c5, c0, 1 // CS0-4: full access
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mcr 15, 0, r0, c5, c0, 0 // DS0-4: full access
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mrc 15, 0, r0, c1, c0, 0
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orr r0, r0, #0x5
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orr r0, r0, #0x1000
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mcr 15, 0, r0, c1, c0, 0 // re-enable protection unit and caches
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ldr r1, =0x38200000
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ldr r0, =0x006A49A5 // default: settings from Apple FW (96 MHz HCLK)
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str r0, [r1, #0x10] // MIUSDPARA
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#else
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ldr r1, =0x3c500000
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mov r0, #0 // 0x0
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str r0, [r1, #40] // enable clock for all peripherals
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mov r0, #0 // 0x0
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str r0, [r1, #44] // do not enter any power saving mode
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#if defined(MEIZU_M6SP) || defined(MEIZU_M3)
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/* setup SDRAM for Meizu M6SP */
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ldr r1, =0x38200000
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// configure SDR drive strength and pad settings
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mov r0, #SDR_DSS_SEL_B
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str r0, [r1, #0x4C] // MIU_DSS_SEL_B
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mov r0, #SDR_DSS_SEL_O
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str r0, [r1, #0x50] // MIU_DSS_SEL_O
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mov r0, #SDR_DSS_SEL_C
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str r0, [r1, #0x54] // MIU_DSS_SEL_C
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mov r0, #2
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str r0, [r1, #0x60] // SSTL2_PAD_ON
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// select SDR mode
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ldr r0, [r1, #0x40]
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mov r2, #0xFFFDFFFF
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and r0, r0, r2
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orr r0, r0, #1
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str r0, [r1, #0x40] // MIUORG
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// set controller configuration
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mov r0, #SDR_CONFIG
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str r0, [r1] // MIUCON
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// set SDRAM timing
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ldr r0, =SDR_TIMING
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str r0, [r1, #0x10] // MIUSDPARA
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// set refresh rate
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mov r0, #0x1080
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str r0, [r1, #0x08] // MIUAREF
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// initialise SDRAM
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mov r0, #0x003
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str r0, [r1, #0x04] // MIUCOM = nop
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ldr r0, =0x203
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str r0, [r1, #0x04] // MIUCOM = precharge all banks
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nop
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nop
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nop
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ldr r0, =0x303
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str r0, [r1, #0x04] // MIUCOM = auto-refresh
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nop
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nop
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nop
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nop
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str r0, [r1, #0x04] // MIUCOM = auto-refresh
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nop
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nop
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nop
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nop
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str r0, [r1, #0x04] // MIUCOM = auto-refresh
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nop
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nop
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nop
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nop
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// set mode register
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mov r0, #SDR_MRS
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str r0, [r1, #0x0C] // MIUMRS
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ldr r0, =0x103
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str r0, [r1, #0x04] // MIUCOM = mode register set
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ldr r0, =SDR_EMRS
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str r0, [r1, #0x0C] // MIUMRS
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ldr r0, =0x103
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str r0, [r1, #0x04] // MIUCOM = mode register set
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#endif /* MEIZU_M6SP */
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mov r1, #0x1
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mrc 15, 0, r0, c1, c0, 0
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bic r0, r0, r1
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mcr 15, 0, r0, c1, c0, 0 // disable protection unit
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mov r1, #0x4
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mrc 15, 0, r0, c1, c0, 0
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bic r0, r0, r1
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mcr 15, 0, r0, c1, c0, 0 // dcache disable
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mov r1, #0x1000
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mrc 15, 0, r0, c1, c0, 0
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bic r0, r0, r1
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mcr 15, 0, r0, c1, c0, 0 // icache disable
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mov r1, #0
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1:
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mov r0, #0
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2:
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orr r2, r1, r0
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mcr 15, 0, r2, c7, c14, 2 // clean and flush dcache single entry
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add r0, r0, #0x10
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cmp r0, #0x40
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bne 2b
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add r1, r1, #0x4000000
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cmp r1, #0x0
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bne 1b
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nop
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nop
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mov r0, #0
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mcr 15, 0, r0, c7, c10, 4 // clean and flush whole dcache
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mov r0, #0
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mcr 15, 0, r0, c7, c5, 0 // flush icache
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mov r0, #0
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mcr 15, 0, r0, c7, c6, 0 // flush dcache
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mov r0, #0x3f
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mcr 15, 0, r0, c6, c0, 1
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mov r0, #0x2f
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mcr 15, 0, r0, c6, c1, 1
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ldr r0, =0x08000031
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mcr 15, 0, r0, c6, c2, 1
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ldr r0, =0x22000023
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mcr 15, 0, r0, c6, c3, 1
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ldr r0, =0x24000027
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mcr 15, 0, r0, c6, c4, 1
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mov r0, #0x3f
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mcr 15, 0, r0, c6, c0, 0
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mov r0, #0x2f
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mcr 15, 0, r0, c6, c1, 0
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ldr r0, =0x08000031
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mcr 15, 0, r0, c6, c2, 0
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ldr r0, =0x22000023
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mcr 15, 0, r0, c6, c3, 0
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ldr r0, =0x24000029
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mcr 15, 0, r0, c6, c4, 0
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mov r0, #0x1e
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mcr 15, 0, r0, c2, c0, 1
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mov r0, #0x1e
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mcr 15, 0, r0, c2, c0, 0
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mov r0, #0x1e
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mcr 15, 0, r0, c3, c0, 0
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ldr r0, =0x0000ffff
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mcr 15, 0, r0, c5, c0, 1
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ldr r0, =0x0000ffff
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mcr 15, 0, r0, c5, c0, 0 // set up protection and caching
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mov r1, #0x4
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mrc 15, 0, r0, c1, c0, 0
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orr r0, r0, r1
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mcr 15, 0, r0, c1, c0, 0 // dcache enable
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mov r1, #0x1000
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mrc 15, 0, r0, c1, c0, 0
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orr r0, r0, r1
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mcr 15, 0, r0, c1, c0, 0 // icache enable
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mov r1, #0x1
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mrc 15, 0, r0, c1, c0, 0
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orr r0, r0, r1
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mcr 15, 0, r0, c1, c0, 0 // enable protection unit
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#endif
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#if CONFIG_CPU==S5L8700 || !defined(BOOTLOADER)
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/* Copy interrupt vectors to iram */
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ldr r2, =_intvectstart
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ldr r3, =_intvectend
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ldr r4, =_intvectcopy
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1:
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cmp r3, r2
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ldrhi r1, [r4], #4
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strhi r1, [r2], #4
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bhi 1b
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#endif
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/* Initialise bss section to zero */
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ldr r2, =_edata
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ldr r3, =_end
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mov r4, #0
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1:
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cmp r3, r2
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strhi r4, [r2], #4
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bhi 1b
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#if CONFIG_CPU==S5L8700 && defined(BOOTLOADER)
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/* Copy icode and data to ram */
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ldr r2, =_datastart
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ldr r3, =_dataend
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ldr r4, =_datacopy
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1:
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cmp r3, r2
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ldrhi r1, [r4], #4
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strhi r1, [r2], #4
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bhi 1b
|
|
#endif
|
|
|
|
#ifndef BOOTLOADER
|
|
/* Copy icode and data to ram */
|
|
ldr r2, =_iramstart
|
|
ldr r3, =_iramend
|
|
ldr r4, =_iramcopy
|
|
1:
|
|
cmp r3, r2
|
|
ldrhi r1, [r4], #4
|
|
strhi r1, [r2], #4
|
|
bhi 1b
|
|
|
|
/* Initialise ibss section to zero */
|
|
ldr r2, =_iedata
|
|
ldr r3, =_iend
|
|
mov r4, #0
|
|
1:
|
|
cmp r3, r2
|
|
strhi r4, [r2], #4
|
|
bhi 1b
|
|
#endif
|
|
|
|
/* Set up some stack and munge it with 0xdeadbeef */
|
|
ldr sp, =stackend
|
|
ldr r2, =stackbegin
|
|
ldr r3, =0xdeadbeef
|
|
1:
|
|
cmp sp, r2
|
|
strhi r3, [r2], #4
|
|
bhi 1b
|
|
|
|
/* Set up stack for IRQ mode */
|
|
msr cpsr_c, #0xd2
|
|
ldr sp, =_irqstackend
|
|
|
|
/* Set up stack for FIQ mode */
|
|
msr cpsr_c, #0xd1
|
|
ldr sp, =_fiqstackend
|
|
|
|
/* Let abort and undefined modes use IRQ stack */
|
|
msr cpsr_c, #0xd7
|
|
ldr sp, =_irqstackend
|
|
msr cpsr_c, #0xdb
|
|
ldr sp, =_irqstackend
|
|
|
|
/* Switch back to supervisor mode */
|
|
msr cpsr_c, #0xd3
|
|
|
|
// if we did not switch remap on, device
|
|
// would crash when MENU is pressed,
|
|
// as that button is connected to BOOT_MODE pin
|
|
#if CONFIG_CPU==S5L8700
|
|
ldr r1, =0x38200000
|
|
ldr r0, [r1]
|
|
mvn r2, #0x10000
|
|
and r0, r0, r2
|
|
mov r2, #0x1
|
|
orr r0, r0, r2
|
|
str r0, [r1] // remap iram to address 0x0
|
|
#endif
|
|
|
|
bl main
|
|
|
|
.text
|
|
/* .global UIE*/
|
|
|
|
/* All illegal exceptions call into UIE with exception address as first
|
|
* parameter. This is calculated differently depending on which exception
|
|
* we're in. Second parameter is exception number, used for a string lookup
|
|
* in UIE. */
|
|
undef_instr_handler:
|
|
sub r0, lr, #4
|
|
mov r1, #0
|
|
b UIE
|
|
|
|
/* We run supervisor mode most of the time, and should never see a software
|
|
* exception being thrown. Perhaps make it illegal and call UIE? */
|
|
software_int_handler:
|
|
reserved_handler:
|
|
movs pc, lr
|
|
|
|
prefetch_abort_handler:
|
|
sub r0, lr, #4
|
|
mov r1, #1
|
|
b UIE
|
|
|
|
data_abort_handler:
|
|
sub r0, lr, #8
|
|
mov r1, #2
|
|
b UIE
|