507 lines
16 KiB
C
507 lines
16 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2014 by Cástor Muñoz
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include <stdint.h>
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#include <stdbool.h>
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#include "config.h"
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#include "system.h"
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#include "uart-target.h"
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#include "uc870x.h"
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/*
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* UC870x: UART controller for s5l870x
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*/
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/* Rx related masks */
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#if CONFIG_CPU == S5L8700
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#define UTRSTAT_RX_RELATED_INTS (UTRSTAT_RX_INT_BIT | UTRSTAT_ERR_INT_BIT)
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#define UCON_RX_RELATED_INTS (UCON_RX_INT_BIT | UCON_ERR_INT_BIT)
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#elif CONFIG_CPU == S5L8701
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#define UTRSTAT_RX_RELATED_INTS \
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(UTRSTAT_RX_INT_BIT | UTRSTAT_ERR_INT_BIT | UTRSTAT_AUTOBR_INT_BIT)
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#define UCON_RX_RELATED_INTS \
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(UCON_RX_INT_BIT | UCON_ERR_INT_BIT | UCON_AUTOBR_INT_BIT)
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#else /* CONFIG_CPU == S5L8702 */
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#define UTRSTAT_RX_RELATED_INTS \
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(UTRSTAT_RX_INT_BIT | UTRSTAT_ERR_INT_BIT | \
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UTRSTAT_AUTOBR_INT_BIT | UTRSTAT_RX_TOUT_INT_BIT)
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#define UCON_RX_RELATED_INTS \
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(UCON_RX_INT_BIT | UCON_ERR_INT_BIT | \
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UCON_AUTOBR_INT_BIT | UCON_RX_TOUT_INT_BIT)
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#endif
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#define UART_PORT_BASE(u,i) (((u)->baddr) + (u)->port_off * (i))
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/* Initialization */
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static void uartc_reset_port_id(const struct uartc* uartc, int port_id)
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{
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uart_target_disable_irq(uartc->id, port_id);
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uart_target_disable_gpio(uartc->id, port_id);
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/* set port registers to default reset values */
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uint32_t baddr = UART_PORT_BASE(uartc, port_id);
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UCON(baddr) = 0;
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ULCON(baddr) = 0;
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UMCON(baddr) = 0;
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UFCON(baddr) = UFCON_RX_FIFO_RST_BIT | UFCON_TX_FIFO_RST_BIT;
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UTRSTAT(baddr) = ~0; /* clear all interrupts */
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UBRDIV(baddr) = 0;
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#if CONFIG_CPU == S5L8702
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UBRCONTX(baddr) = 0;
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UBRCONRX(baddr) = 0;
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#endif
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uartc->port_l[port_id] = (void*)0;
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}
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static void uartc_reset(const struct uartc* uartc)
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{
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for (int port_id = 0; port_id < uartc->n_ports; port_id++)
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uartc_reset_port_id(uartc, port_id);
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}
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void uartc_open(const struct uartc *uartc)
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{
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uart_target_enable_clocks(uartc->id);
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uartc_reset(uartc);
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}
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void uartc_close(const struct uartc *uartc)
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{
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uartc_reset(uartc);
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uart_target_disable_clocks(uartc->id);
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}
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void uartc_port_open(struct uartc_port *port)
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{
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const struct uartc *uartc = port->uartc;
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uint32_t baddr = UART_PORT_BASE(uartc, port->id);
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uart_target_enable_gpio(uartc->id, port->id);
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/* disable Tx/Rx and mask all interrupts */
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UCON(baddr) = 0;
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/* clear all interrupts */
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UTRSTAT(baddr) = ~0;
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/* configure registers */
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UFCON(baddr) = UFCON_FIFO_ENABLE_BIT
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| UFCON_RX_FIFO_RST_BIT
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| UFCON_TX_FIFO_RST_BIT
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| ((port->rx_trg & UFCON_RX_FIFO_TRG_MASK) << UFCON_RX_FIFO_TRG_POS)
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| ((port->tx_trg & UFCON_TX_FIFO_TRG_MASK) << UFCON_TX_FIFO_TRG_POS);
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UMCON(baddr) = UMCON_RTS_BIT; /* activate nRTS (low level) */
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UCON(baddr) = (UCON_MODE_DISABLED << UCON_RX_MODE_POS)
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| (UCON_MODE_DISABLED << UCON_TX_MODE_POS)
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| ((port->clksel & UCON_CLKSEL_MASK) << UCON_CLKSEL_POS)
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| (port->rx_cb ? UCON_RX_RELATED_INTS|UCON_RX_TOUT_EN_BIT : 0)
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| (port->tx_cb ? UCON_TX_INT_BIT : 0);
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/* init and register port struct */
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port->baddr = baddr;
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port->utrstat_int_mask = (port->rx_cb ? UTRSTAT_RX_RELATED_INTS : 0)
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| (port->tx_cb ? UTRSTAT_TX_INT_BIT : 0);
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#if CONFIG_CPU != S5L8700
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port->abr_aborted = 0;
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#endif
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uartc->port_l[port->id] = port;
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/* enable interrupts */
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uart_target_clear_irq(uartc->id, port->id);
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/*if (port->utrstat_int_mask)*/
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uart_target_enable_irq(uartc->id, port->id);
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}
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void uartc_port_close(struct uartc_port *port)
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{
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uartc_reset_port_id(port->uartc, port->id);
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}
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/* Configuration */
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void uartc_port_config(struct uartc_port *port,
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uint8_t data_bits, uint8_t parity, uint8_t stop_bits)
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{
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ULCON(port->baddr) = ((parity & ULCON_PARITY_MASK) << ULCON_PARITY_POS)
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| ((stop_bits & ULCON_STOP_BITS_MASK) << ULCON_STOP_BITS_POS)
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| ((data_bits & ULCON_DATA_BITS_MASK) << ULCON_DATA_BITS_POS);
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}
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/* set bitrate using precalculated values */
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void uartc_port_set_bitrate_raw(struct uartc_port *port, uint32_t brdata)
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{
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uint32_t baddr = port->baddr;
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UBRDIV(baddr) = brdata & 0xff;
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#if CONFIG_CPU == S5L8702
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UBRCONRX(baddr) = brdata >> 8;
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UBRCONTX(baddr) = brdata >> 8;
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#endif
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}
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#if 0
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/* calculate values to set real bitrate as close as possible to the
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requested speed */
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void uartc_port_set_bitrate(struct uartc_port *port, unsigned int speed)
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{
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int uclk = port->clkhz;
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/* Real baud width in UCLK/16 ticks: trunc(UCLK/(16*speed) + 0.5) */
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int brdiv = (uclk + (speed << 3)) / (speed << 4);
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uint32_t brdata = brdiv - 1;
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#if CONFIG_CPU == S5L8702
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/* Fine adjust:
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*
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* Along the whole frame, insert/remove "jittered" bauds when needed
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* to minimize frame lenght accumulated error.
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*
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* jitter_width: "jittered" bauds are 1/16 wider/narrower than normal
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* bauds, so step is 1/16 of real baud width = brdiv (in UCLK ticks)
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*
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* baud_err_width: it is the difference between theoric width and real
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* width = CLK/speed - brdiv*16 (in UCLK ticks)
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*
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* Previous widths are scaled by 'speed' factor to simplify operations
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* and preserve precision using integer operations.
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*/
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int jitter_width = brdiv * speed;
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int baud_err_width = uclk - (jitter_width << 4);
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int jitter_incdec = UBRCON_JITTER_INC;
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if (baud_err_width < 0) {
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baud_err_width = -baud_err_width;
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jitter_incdec = UBRCON_JITTER_DEC;
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}
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int err_width = 0;
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uint32_t brcon = 0;
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for (int bit = 0; bit < UC_FRAME_MAX_LEN; bit++) {
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err_width += baud_err_width;
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/* adjust to the nearest width */
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if (jitter_width < (err_width << 1)) {
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brcon |= jitter_incdec << UBRCON_JITTER_POS(bit);
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err_width -= jitter_width;
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}
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}
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brdata |= (brcon << 8);
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#endif /* CONFIG_CPU == S5L8702 */
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uartc_port_set_rawbr(port, brdata);
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}
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#endif
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/* Select Tx/Rx modes: disabling Tx/Rx resets HW, including
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FIFOs and shift registers */
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void uartc_port_set_rx_mode(struct uartc_port *port, uint32_t mode)
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{
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UCON(port->baddr) = (mode << UCON_RX_MODE_POS) |
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(_UCON_RD(port->baddr) & ~(UCON_RX_MODE_MASK << UCON_RX_MODE_POS));
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}
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void uartc_port_set_tx_mode(struct uartc_port *port, uint32_t mode)
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{
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UCON(port->baddr) = (mode << UCON_TX_MODE_POS) |
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(_UCON_RD(port->baddr) & ~(UCON_TX_MODE_MASK << UCON_TX_MODE_POS));
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}
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/* Transmit */
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bool uartc_port_tx_ready(struct uartc_port *port)
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{
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return (UTRSTAT(port->baddr) & UTRSTAT_TXBUF_EMPTY_BIT);
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}
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void uartc_port_tx_byte(struct uartc_port *port, uint8_t ch)
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{
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UTXH(port->baddr) = ch;
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#ifdef UC870X_DEBUG
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port->n_tx_bytes++;
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#endif
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}
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void uartc_port_send_byte(struct uartc_port *port, uint8_t ch)
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{
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/* wait for transmit buffer empty */
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while (!uartc_port_tx_ready(port));
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uartc_port_tx_byte(port, ch);
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}
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/* Receive */
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bool uartc_port_rx_ready(struct uartc_port *port)
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{
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/* test receive buffer data ready */
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return (UTRSTAT(port->baddr) & UTRSTAT_RXBUF_RDY_BIT);
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}
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uint8_t uartc_port_rx_byte(struct uartc_port *port)
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{
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return URXH(port->baddr) & 0xff;
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}
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uint8_t uartc_port_read_byte(struct uartc_port *port)
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{
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while (!uartc_port_rx_ready(port));
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return uartc_port_rx_byte(port);
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}
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#if CONFIG_CPU != S5L8700
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/* Autobauding */
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static inline int uartc_port_abr_status(struct uartc_port *port)
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{
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return UABRSTAT(port->baddr) & UABRSTAT_STATUS_MASK;
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}
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void uartc_port_abr_start(struct uartc_port *port)
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{
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port->abr_aborted = 0;
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UCON(port->baddr) = _UCON_RD(port->baddr) | UCON_AUTOBR_START_BIT;
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}
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void uartc_port_abr_stop(struct uartc_port *port)
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{
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if (uartc_port_abr_status(port) == UABRSTAT_STATUS_COUNTING)
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/* There is no known way to stop the HW once COUNTING is
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* in progress.
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* If we disable AUTOBR_START_BIT now, COUNTING is not
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* aborted, instead the HW will launch interrupts for
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* every new rising edge detected while AUTOBR_START_BIT
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* remains disabled.
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* If AUTOBR_START_BIT is enabled, the HW will stop by
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* itself when a rising edge is detected.
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* So, do not disable AUTOBR_START_BIT and wait for the
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* next rising edge.
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*/
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port->abr_aborted = 1;
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else
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UCON(port->baddr) = _UCON_RD(port->baddr) & ~UCON_AUTOBR_START_BIT;
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}
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#endif /* CONFIG_CPU != S5L8700 */
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/* ISR */
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void ICODE_ATTR uartc_callback(const struct uartc* uartc, int port_id)
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{
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struct uartc_port *port = uartc->port_l[port_id];
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uint32_t baddr = port->baddr;
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/* filter registered interrupts */
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uint32_t ints = UTRSTAT(baddr) & port->utrstat_int_mask;
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/* clear interrupts, events ocurring while processing
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this ISR will be processed in the next call */
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UTRSTAT(baddr) = ints;
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if (ints & UTRSTAT_RX_RELATED_INTS)
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{
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int len = 0;
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#if CONFIG_CPU != S5L8700
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uint32_t abr_cnt = 0;
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if (ints & UTRSTAT_AUTOBR_INT_BIT)
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{
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if (uartc_port_abr_status(port) == UABRSTAT_STATUS_COUNTING) {
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#ifdef UC870X_DEBUG
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if (_UCON_RD(baddr) & UCON_AUTOBR_START_BIT) port->n_abnormal0++;
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else port->n_abnormal1++;
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#endif
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/* try to fix abnormal situations */
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UCON(baddr) = _UCON_RD(baddr) | UCON_AUTOBR_START_BIT;
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}
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else if (!port->abr_aborted)
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abr_cnt = UABRCNT(baddr);
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}
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if (ints & (UTRSTAT_RX_RELATED_INTS ^ UTRSTAT_AUTOBR_INT_BIT))
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#endif /* CONFIG_CPU != S5L8700 */
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{
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/* get FIFO count */
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uint32_t ufstat = UFSTAT(baddr);
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len = (ufstat & UFSTAT_RX_FIFO_CNT_MASK) |
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((ufstat & UFSTAT_RX_FIFO_FULL_BIT) >> (8 - 4));
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for (int i = 0; i < len; i++) {
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/* must read error status first, then data */
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port->rx_err[i] = UERSTAT(baddr);
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port->rx_data[i] = URXH(baddr);
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}
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}
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/* 'len' might be zero due to RX_TOUT interrupts are
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* raised by the hardware even when RX FIFO is empty.
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* When overrun, it is marked on the first error:
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* overrun = len ? (rx_err[0] & UERSTAT_OVERRUN_BIT) : 0
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*/
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#if CONFIG_CPU == S5L8700
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port->rx_cb(len, port->rx_data, port->rx_err);
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#else
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/* 'abr_cnt' is zero when no ABR interrupt exists */
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port->rx_cb(len, port->rx_data, port->rx_err, abr_cnt);
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#endif
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#ifdef UC870X_DEBUG
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if (len) {
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port->n_rx_bytes += len;
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if (port->rx_err[0] & UERSTAT_OVERRUN_BIT)
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port->n_ovr_err++;
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for (int i = 0; i < len; i++) {
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if (port->rx_err[i] & UERSTAT_PARITY_ERR_BIT)
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port->n_parity_err++;
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if (port->rx_err[i] & UERSTAT_FRAME_ERR_BIT)
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port->n_frame_err++;
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if (port->rx_err[i] & UERSTAT_BREAK_DETECT_BIT)
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port->n_break_detect++;
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}
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}
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#endif
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}
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#if 0
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/* not used and not tested */
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if (ints & UTRSTAT_TX_INT_BIT)
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{
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port->tx_cb(UART_FIFO_SIZE - ((UFSTAT(baddr) & \
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UFSTAT_TX_FIFO_CNT_MASK) >> UFSTAT_TX_FIFO_CNT_POS));
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}
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#endif
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}
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#ifdef UC870X_DEBUG
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/*#define LOGF_ENABLE*/
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#include "logf.h"
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#if CONFIG_CPU == S5L8702
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static int get_bitrate(int uclk, int brdiv, int brcon, int frame_len)
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{
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logf("get_bitrate(%d, %d, 0x%08x, %d)", uclk, brdiv, brcon, frame_len);
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int avg_speed;
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int speed_sum = 0;
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unsigned int frame_width = 0; /* in UCLK clock ticks */
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/* calculate resulting speed for every frame len */
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for (int bit = 0; bit < frame_len; bit++)
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{
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frame_width += brdiv * 16;
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int incdec = ((brcon >> UBRCON_JITTER_POS(bit)) & UBRCON_JITTER_MASK);
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if (incdec == UBRCON_JITTER_INC) frame_width += brdiv;
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else if (incdec == UBRCON_JITTER_DEC) frame_width -= brdiv;
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/* speed = truncate((UCLK / (real_frame_width / NBITS)) + 0.5)
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XXX: overflows for big UCLK */
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int speed = (((uclk*(bit+1))<<1) + frame_width) / (frame_width<<1);
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speed_sum += speed;
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logf(" %d: %c %d", bit, ((incdec == UBRCON_JITTER_INC) ? 'i' :
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((incdec == UBRCON_JITTER_DEC) ? 'd' : '.')), speed);
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}
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/* average of the speed for all frame lengths */
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avg_speed = speed_sum / frame_len;
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logf(" avg speed = %d", avg_speed);
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return avg_speed;
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}
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#endif /* CONFIG_CPU == S5L8702 */
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void uartc_port_get_line_info(struct uartc_port *port,
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int *tx_status, int *rx_status,
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int *tx_speed, int *rx_speed, char *line_cfg)
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{
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uint32_t baddr = port->baddr;
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uint32_t ucon = _UCON_RD(baddr);
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if (tx_status)
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*tx_status = ((ucon >> UCON_TX_MODE_POS) & UCON_TX_MODE_MASK) ? 1 : 0;
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if (rx_status)
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*rx_status = ((ucon >> UCON_RX_MODE_POS) & UCON_RX_MODE_MASK) ? 1 : 0;
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uint32_t ulcon = ULCON(baddr);
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int n_data = ((ulcon >> ULCON_DATA_BITS_POS) & ULCON_DATA_BITS_MASK) + 5;
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int n_stop = ((ulcon >> ULCON_STOP_BITS_POS) & ULCON_STOP_BITS_MASK) + 1;
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int parity = (ulcon >> ULCON_PARITY_POS) & ULCON_PARITY_MASK;
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uint32_t brdiv = UBRDIV(baddr) + 1;
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#if CONFIG_CPU == S5L8702
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int frame_len = 1 + n_data + (parity ? 1 : 0) + n_stop;
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if (tx_speed)
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*tx_speed = get_bitrate(port->clkhz, brdiv, UBRCONTX(baddr), frame_len);
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if (rx_speed)
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*rx_speed = get_bitrate(port->clkhz, brdiv, UBRCONRX(baddr), frame_len);
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#else
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/* speed = truncate(UCLK/(16*brdiv) + 0.5) */
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int speed = (port->clkhz + (brdiv << 3)) / (brdiv << 4);
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if (tx_speed) *tx_speed = speed;
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if (rx_speed) *rx_speed = speed;
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#endif
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|
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if (line_cfg) {
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line_cfg[0] = '0' + n_data;
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line_cfg[1] = ((parity == ULCON_PARITY_NONE) ? 'N' :
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((parity == ULCON_PARITY_EVEN) ? 'E' :
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((parity == ULCON_PARITY_ODD) ? 'O' :
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((parity == ULCON_PARITY_FORCE_1) ? 'M' :
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((parity == ULCON_PARITY_FORCE_0) ? 'S' : '?')))));
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line_cfg[2] = '0' + n_stop;
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line_cfg[3] = '\0';
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}
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}
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|
|
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#if CONFIG_CPU != S5L8700
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/* Autobauding */
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int uartc_port_get_abr_info(struct uartc_port *port, uint32_t *abr_cnt)
|
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{
|
|
int status;
|
|
uint32_t abr_status;
|
|
|
|
int flags = disable_irq_save();
|
|
|
|
abr_status = uartc_port_abr_status(port);
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|
|
|
if (_UCON_RD(port->baddr) & UCON_AUTOBR_START_BIT) {
|
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if (abr_status == UABRSTAT_STATUS_COUNTING)
|
|
status = ABR_INFO_ST_COUNTING; /* waiting for rising edge */
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else
|
|
status = ABR_INFO_ST_LAUNCHED; /* waiting for falling edge */
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|
}
|
|
else {
|
|
if (abr_status == UABRSTAT_STATUS_COUNTING)
|
|
status = ABR_INFO_ST_ABNORMAL;
|
|
else
|
|
status = ABR_INFO_ST_IDLE;
|
|
}
|
|
|
|
if (abr_cnt)
|
|
*abr_cnt = UABRCNT(port->baddr);
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|
|
|
restore_irq(flags);
|
|
|
|
return status;
|
|
}
|
|
#endif /* CONFIG_CPU != S5L8700 */
|
|
#endif /* UC870X_DEBUG */
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