275 lines
8.4 KiB
C
275 lines
8.4 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2007 by Rob Purchase
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* Copyright © 2008 Rafaël Carré
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include "kernel.h"
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#include "system.h"
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#include "panic.h"
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#include "ascodec-target.h"
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#include "dma-target.h"
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#define default_interrupt(name) \
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extern __attribute__((weak,alias("UIRQ"))) void name (void)
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void irq_handler(void) __attribute__((interrupt ("IRQ"), naked));
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void fiq_handler(void) __attribute__((interrupt ("FIQ"), naked));
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default_interrupt(INT_WATCHDOG);
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default_interrupt(INT_TIMER1);
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default_interrupt(INT_TIMER2);
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default_interrupt(INT_USB);
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default_interrupt(INT_DMAC);
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default_interrupt(INT_NAND);
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default_interrupt(INT_IDE);
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default_interrupt(INT_MCI0);
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default_interrupt(INT_MCI1);
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default_interrupt(INT_AUDIO);
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default_interrupt(INT_SSP);
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default_interrupt(INT_I2C_MS);
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default_interrupt(INT_I2C_AUDIO);
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default_interrupt(INT_I2SIN);
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default_interrupt(INT_I2SOUT);
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default_interrupt(INT_UART);
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default_interrupt(INT_GPIOD);
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default_interrupt(RESERVED1); /* Interrupt 17 : unused */
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default_interrupt(INT_CGU);
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default_interrupt(INT_MEMORY_STICK);
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default_interrupt(INT_DBOP);
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default_interrupt(RESERVED2); /* Interrupt 21 : unused */
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default_interrupt(RESERVED3); /* Interrupt 22 : unused */
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default_interrupt(RESERVED4); /* Interrupt 23 : unused */
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default_interrupt(RESERVED5); /* Interrupt 24 : unused */
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default_interrupt(RESERVED6); /* Interrupt 25 : unused */
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default_interrupt(RESERVED7); /* Interrupt 26 : unused */
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default_interrupt(RESERVED8); /* Interrupt 27 : unused */
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default_interrupt(RESERVED9); /* Interrupt 28 : unused */
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default_interrupt(INT_GPIOA);
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default_interrupt(INT_GPIOB);
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default_interrupt(INT_GPIOC);
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static void (* const irqvector[])(void) =
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{
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INT_WATCHDOG, INT_TIMER1, INT_TIMER2, INT_USB, INT_DMAC, INT_NAND, INT_IDE, INT_MCI0,
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INT_MCI1, INT_AUDIO, INT_SSP, INT_I2C_MS, INT_I2C_AUDIO, INT_I2SIN, INT_I2SOUT,
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INT_UART, INT_GPIOD, RESERVED1 /* 17 */ ,INT_CGU, INT_MEMORY_STICK, INT_DBOP,
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RESERVED2 /* 21 */, RESERVED3 /* 22 */, RESERVED4 /* 23 */, RESERVED5 /* 24 */,
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RESERVED6 /* 25 */, RESERVED7 /* 26 */, RESERVED8 /* 27 */, RESERVED9 /* 28 */,
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INT_GPIOA, INT_GPIOB, INT_GPIOC
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};
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static const char * const irqname[] =
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{
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"INT_WATCHDOG", "INT_TIMER1", "INT_TIMER2", "INT_USB", "INT_DMAC", "INT_NAND",
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"INT_IDE", "INT_MCI0", "INT_MCI1", "INT_AUDIO", "INT_SSP", "INT_I2C_MS",
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"INT_I2C_AUDIO", "INT_I2SIN", "INT_I2SOUT", "INT_UART", "INT_GPIOD", "RESERVED1",
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"INT_CGU", "INT_MEMORY_STICK", "INT_DBOP", "RESERVED2", "RESERVED3", "RESERVED4",
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"RESERVED5", "RESERVED6", "RESERVED7", "RESERVED8", "RESERVED9", "INT_GPIOA",
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"INT_GPIOB", "INT_GPIOC"
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};
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static void UIRQ(void)
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{
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unsigned int irq_no = 0;
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int status = VIC_IRQ_STATUS;
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while((status >>= 1))
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irq_no++;
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panicf("Unhandled IRQ %02X: %s", irq_no, irqname[irq_no]);
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}
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void irq_handler(void)
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{
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/*
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* Based on: linux/arch/arm/kernel/entry-armv.S and system-meg-fx.c
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*/
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asm volatile( "stmfd sp!, {r0-r7, ip, lr} \n" /* Store context */
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"sub sp, sp, #8 \n"); /* Reserve stack */
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unsigned int irq_no = 0;
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int status = VIC_IRQ_STATUS;
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while((status >>= 1))
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irq_no++;
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irqvector[irq_no]();
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asm volatile( "add sp, sp, #8 \n" /* Cleanup stack */
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"ldmfd sp!, {r0-r7, ip, lr} \n" /* Restore context */
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"subs pc, lr, #4 \n"); /* Return from IRQ */
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}
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void fiq_handler(void)
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{
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asm volatile (
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"subs pc, lr, #4 \r\n"
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);
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}
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#ifdef BOOTLOADER
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static void sdram_delay(void)
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{
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int delay = 1024; /* arbitrary */
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while (delay--) ;
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}
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/* Use the same initialization than OF */
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static void sdram_init(void)
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{
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CGU_PERI &= ~(0xf<<2); /* clear div0 (memclock) */
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CGU_PERI |= (1<<2); /* divider = 2 */
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CGU_PERI |= (1<<26)|(1<<27); /* extmem & extmem intf clocks */
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MPMC_CONTROL = 0x1; /* enable MPMC */
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MPMC_DYNAMIC_CONTROL = 0x183; /* SDRAM NOP, all clocks high */
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sdram_delay();
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MPMC_DYNAMIC_CONTROL = 0x103; /* SDRAM PALL, all clocks high */
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sdram_delay();
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MPMC_DYNAMIC_REFRESH = 0x138; /* 0x138 * 16 HCLK ticks between SDRAM refresh cycles */
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MPMC_CONFIG = 0; /* little endian, HCLK:MPMCCLKOUT[3:0] ratio = 1:1 */
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if(MPMC_PERIPH_ID2 & 0xf0)
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MPMC_DYNAMIC_READ_CONFIG = 0x1; /* command delayed, clock out not delayed */
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/* timings */
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MPMC_DYNAMIC_tRP = 2;
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MPMC_DYNAMIC_tRAS = 4;
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MPMC_DYNAMIC_tSREX = 5;
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MPMC_DYNAMIC_tAPR = 0;
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MPMC_DYNAMIC_tDAL = 4;
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MPMC_DYNAMIC_tWR = 2;
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MPMC_DYNAMIC_tRC = 5;
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MPMC_DYNAMIC_tRFC = 5;
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MPMC_DYNAMIC_tXSR = 5;
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MPMC_DYNAMIC_tRRD = 2;
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MPMC_DYNAMIC_tMRD = 2;
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#if defined(SANSA_CLIP) || defined(SANSA_M200V4)
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/* 16 bits external bus, low power SDRAM, 16 Mbits = 2 Mbytes */
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#define MEMORY_MODEL 0x21
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#elif defined(SANSA_E200V2) || defined(SANSA_FUZE)
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/* 16 bits external bus, high performance SDRAM, 64 Mbits = 8 Mbytes */
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#define MEMORY_MODEL 0x5
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#else
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#error "The external memory in your player is unknown"
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#endif
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MPMC_DYNAMIC_RASCAS_0 = (2<<8)|2; /* CAS & RAS latency = 2 clock cycles */
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MPMC_DYNAMIC_CONFIG_0 = (MEMORY_MODEL << 7);
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MPMC_DYNAMIC_RASCAS_1 = MPMC_DYNAMIC_CONFIG_1 =
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MPMC_DYNAMIC_RASCAS_2 = MPMC_DYNAMIC_CONFIG_2 =
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MPMC_DYNAMIC_RASCAS_3 = MPMC_DYNAMIC_CONFIG_3 = 0;
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MPMC_DYNAMIC_CONTROL = 0x82; /* SDRAM MODE, MPMCCLKOUT runs continuously */
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/* this part is required, if you know why please explain */
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unsigned int tmp = *(volatile unsigned int*)(0x30000000+0x2300*MEM);
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(void)tmp; /* we just need to read from this location */
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MPMC_DYNAMIC_CONTROL = 0x2; /* SDRAM NORMAL, MPMCCLKOUT runs continuously */
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MPMC_DYNAMIC_CONFIG_0 |= (1<<19); /* buffer enable */
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}
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#endif
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void system_init(void)
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{
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#ifdef BOOTLOADER
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#if 0 /* the GPIO clock is already enabled by the dualboot function */
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CGU_PERI |= CGU_GPIO_CLOCK_ENABLE;
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#endif
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CGU_PROC = 0; /* fclk 24 MHz */
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CGU_PERI &= ~0x7f; /* pclk 24 MHz */
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asm volatile(
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"mrc p15, 0, r0, c1, c0 \n"
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"orr r0, r0, #0xC0000000 \n" /* asynchronous clocking */
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"mcr p15, 0, r0, c1, c0 \n"
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: : : "r0" );
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CGU_PLLA = 0x4330; /* PLLA 384 MHz */
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while(!(CGU_INTCTRL & (1<<0))); /* wait until PLLA is locked */
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CGU_PROC = (3<<2)|0x01; /* fclk = PLLA*5/8 = 240 MHz */
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asm volatile(
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"mov r0, #0 \n"
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"mcr p15, 0, r0, c7, c7 \n" /* invalidate icache & dcache */
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"mrc p15, 0, r0, c1, c0 \n" /* control register */
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"orr r0, r0, #0x1000 \n" /* enable icache */
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"orr r0, r0, #4 \n" /* enable dcache */
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"mcr p15, 0, r0, c1, c0 \n"
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: : : "r0" );
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sdram_init();
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CGU_PERI |= (5<<2)|0x01; /* pclk = PLLA / 6 = 64 MHz */
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/* enable timer interface for TIMER1 & TIMER2 */
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CGU_PERI |= CGU_TIMERIF_CLOCK_ENABLE;
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/* enable VIC */
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VIC_INT_ENABLE = 0; /* disable all interrupt lines */
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CGU_PERI |= CGU_VIC_CLOCK_ENABLE;
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VIC_INT_SELECT = 0; /* only IRQ, no FIQ */
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enable_irq();
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#else
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/* Disable fast hardware power-off, to use power button normally
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* We don't need the power button in the bootloader. */
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ascodec_init();
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ascodec_write(AS3514_CVDD_DCDC3, ascodec_read(AS3514_CVDD_DCDC3) & (1<<2));
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#endif /* BOOTLOADER */
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dma_init();
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}
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void system_reboot(void)
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{
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}
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int system_memory_guard(int newmode)
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{
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(void)newmode;
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return 0;
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}
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#ifndef BOOTLOADER
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#ifdef HAVE_ADJUSTABLE_CPU_FREQ
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void set_cpu_frequency(long frequency)
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{
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/* TODO */
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}
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#endif /* HAVE_ADJUSTABLE_CPU_FREQ */
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#endif /* BOOTLOADER */
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