435 lines
12 KiB
ArmAsm
435 lines
12 KiB
ArmAsm
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2002 by Linus Nielsen Feltzing
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include "config.h"
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#include "cpu.h"
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#if defined(HAVE_BOOTDATA) && !defined(BOOTLOADER)
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#include "bootdata.h"
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#endif
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.section .init.text,"ax",%progbits
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.global start
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start:
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/* PortalPlayer bootloader and startup code based on startup.s from the iPodLinux
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* loader
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*
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* Copyright (c) 2003, Daniel Palffy (dpalffy (at) rainstorm.org)
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* Copyright (c) 2005, Bernard Leach <leachbj@bouncycastle.org>
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*
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*/
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#if CONFIG_CPU == PP5002
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.equ PROC_ID, 0xc4000000
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.equ CPU_ICLR, 0xcf001028
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.equ CPU_CTRL, 0xcf004054
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.equ COP_ICLR, 0xcf001038
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.equ COP_CTRL, 0xcf004058
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.equ CPU_STATUS, 0xcf004050
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.equ COP_STATUS, 0xcf004050
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.equ SLEEP, 0x000000ca
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.equ WAKE, 0x000000ce
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.equ CPUSLEEPING, 0x00008000
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.equ COPSLEEPING, 0x00004000
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.equ CACHE_CTRL, 0xcf004024
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.equ MMAP_LOG, 0xf000f000 /* MMAP0 */
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.equ MMAP_PHYS, 0xf000f004
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#if MEMORYSIZE > 32
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.equ MMAP_MASK, 0x00003c00
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#else
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.equ MMAP_MASK, 0x00003e00
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#endif
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.equ MMAP_FLAGS, 0x00003f84
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#else
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.equ PROC_ID, 0x60000000
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.equ CPU_ICLR, 0x60004028
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.equ CPU_CTRL, 0x60007000
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.equ CPU_STATUS, 0x60007000
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.equ COP_ICLR, 0x60004038
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.equ COP_CTRL, 0x60007004
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.equ COP_STATUS, 0x60007004
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.equ SLEEP, 0x80000000
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.equ WAKE, 0x00000000
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.equ CPUSLEEPING, 0x80000000
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.equ COPSLEEPING, 0x80000000
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.equ CACHE_CTRL, 0x6000c000
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.equ MMAP_LOG, 0xf000f000 /* MMAP0 */
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.equ MMAP_PHYS, 0xf000f004
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#if MEMORYSIZE > 32
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.equ MMAP_MASK, 0x00003c00
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#else
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.equ MMAP_MASK, 0x00003e00
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#endif
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.equ MMAP_FLAGS, 0x00000f84
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#endif
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msr cpsr_c, #0xd3 /* enter supervisor mode, disable IRQ/FIQ */
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b pad_skip
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.space 6*4 /* pad to offset 0x20 */
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.ascii "Rockbox" /* signature for bootloader checking osos */
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.byte 1 /* osos boot version, only 1 exists for now */
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.space 56*4 /* (more than enough) space for exception vectors and mi4 magic */
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pad_skip:
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/* Find out which processor we are - r0 should be preserved for the
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* duration of the init to avoid constant reloading of the processor ID.
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* For each stage, CPU proceeds first, then COP.
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*/
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ldr r0, =PROC_ID
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ldrb r0, [r0]
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/* We need to remap memory from wherever SDRAM is mapped natively, to
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base address 0, so we can put our exception vectors there. We don't
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want to do this remapping while executing from SDRAM, so we copy the
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remapping code to IRAM, then execute from there. Hence, the following
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code is compiled for address 0, but is currently executing at either
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0x28000000 or 0x10000000, depending on chipset version. Do not use any
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absolute addresses until remapping has been done. */
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/* Cores are stepped though the init in turn: CPU then COP. The the remap
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stage is completed by each core in turn and then the COP waits for the
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CPU to finish initializing its kernel where the CPU will wake the COP
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and wait for the COP to finish. This ensures no threading activity
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starts until it is safe. */
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cmp r0, #0x55
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/* mask all interrupt sources before setting anything up */
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ldreq r2, =CPU_ICLR
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ldrne r2, =COP_ICLR
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mvn r1, #0
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str r1, [r2]
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/* put us (co-processor) to sleep and wait for CPU to remap */
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ldrne r2, =COP_CTRL
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movne r1, #SLEEP
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strne r1, [r2]
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nop
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nop
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nop
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/* wait for co-processor to sleep then CPU can begin its remapping */
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ldreq r2, =COP_STATUS
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1:
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ldreq r1, [r2]
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tsteq r1, #COPSLEEPING
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beq 1b
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/* disable cache and local interrupt vectors - it is really not desireable
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to have them enabled here */
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ldr r2, =CACHE_CTRL
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mov r1, #0
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str r1, [r2]
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#if defined(IPOD_VIDEO)
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/* detect 32mb vs 64mb model */
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/* we do this here because after SDRAM is remapped, we already assumed */
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/* its size to be whatever we were compiled for. */
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mov r2, #0x12000000
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mov r3, #64
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strb r3, [r2, #-1] /* first write 64 to last byte of first 32MB bank */
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mov r2, #0x14000000
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mov r3, #32
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strb r3, [r2, #-1] /* now write 32 to last byte of second 32MB bank */
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/* now the last word of the first 32MB bank tells you the RAM size */
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/* since on a 32MB model both writes will touch the same actual location */
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/* this is read later on in boot */
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#endif
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mov r2, #0x40000000
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ldr r3, =remap_start
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ldr r4, =remap_end
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and r6, pc, #0xff000000 /* adjust for execute address */
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orr r3, r3, r6
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orr r4, r4, r6
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/* copy the code to 0x40000000 */
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1:
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ldr r5, [r3], #4
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str r5, [r2], #4
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cmp r3, r4
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blo 1b
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ldr r4, =MMAP_FLAGS
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orr r4, r4, r6 /* adjust for execute address */
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ldr r3, =MMAP_PHYS
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ldr r2, =MMAP_MASK /* ldr is more flexible */
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ldr r1, =MMAP_LOG
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mov pc, #0x40000000
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remap_start:
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str r2, [r1]
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str r4, [r3]
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ldr r1, L_post_remap
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bx r1
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L_post_remap:
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.word remap_end
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remap_end:
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cmp r0, #0x55
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ldr r4, =COP_CTRL
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/* Wakeup co-processor to let it do remappings */
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moveq r3, #WAKE
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/* Sleep us (co-processor) and wait for CPU to do kernel initialization */
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movne r3, #SLEEP
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str r3, [r4]
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nop
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nop
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nop
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/* Jump to co-processor init */
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ldrne pc, =cop_init
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cpu_init:
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/* Wait for COP to go to sleep before proceeding */
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ldr r4, =COP_STATUS
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1:
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ldr r3, [r4]
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tst r3, #COPSLEEPING
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beq 1b
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/* Vectors and IRAM copy is done first since they are reclaimed for
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* other uninitialized sections */
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/* Copy exception handler code to address 0 */
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ldr r2, =_vectorsstart
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ldr r3, =_vectorsend
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ldr r4, =_vectorscopy
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1:
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cmp r3, r2
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ldrhi r5, [r4], #4
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strhi r5, [r2], #4
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bhi 1b
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/* Copy the IRAM */
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ldr r2, =_iramcopy
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ldr r3, =_iramstart
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ldr r4, =_iramend
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1:
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cmp r4, r3
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ldrhi r5, [r2], #4
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strhi r5, [r3], #4
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bhi 1b
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#ifdef HAVE_INIT_ATTR
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/* copy init code to codec buffer */
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ldr r2, =_initstart
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ldr r3, =_initend
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ldr r4, =_initcopy
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1:
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cmp r3, r2
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ldrhi r5, [r4], #4
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strhi r5, [r2], #4
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bhi 1b
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#endif
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/* Zero out IBSS */
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ldr r2, =_iedata
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ldr r3, =_iend
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mov r4, #0
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1:
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cmp r3, r2
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strhi r4, [r2], #4
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bhi 1b
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/* Initialise bss section to zero */
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ldr r2, =_edata
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ldr r3, =_end
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mov r4, #0
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1:
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cmp r3, r2
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strhi r4, [r2], #4
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bhi 1b
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/* Load stack munge value */
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ldr r4, =0xdeadbeef
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#if NUM_CORES > 1
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/* Set up idle stack and munge it with 0xdeadbeef */
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ldr r2, =cpu_idlestackbegin
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ldr r3, =cpu_idlestackend
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1:
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cmp r3, r2
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strhi r4, [r2], #4
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bhi 1b
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#endif
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/* Set up stack for IRQ mode */
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msr cpsr_c, #0x92 /* IRQ disabled, FIQ enabled */
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ldr sp, =irq_stack
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/* Set up stack for FIQ mode */
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msr cpsr_c, #0xd1 /* IRQ/FIQ disabled */
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ldr sp, =fiq_stack
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/* Let svc, abort and undefined modes use irq stack */
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msr cpsr_c, #0xd3 /* IRQ/FIQ disabled */
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ldr sp, =irq_stack
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msr cpsr_c, #0xd7 /* IRQ/FIQ disabled */
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ldr sp, =irq_stack
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msr cpsr_c, #0xdb /* IRQ/FIQ disabled */
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ldr sp, =irq_stack
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/* Switch to sys mode */
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msr cpsr_c, #0xdf
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/* Set up some stack and munge it with 0xdeadbeef */
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ldr r2, =stackbegin
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ldr sp, =stackend
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1:
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cmp sp, r2
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strhi r4, [r2], #4
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bhi 1b
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/* Delay waking the COP until thread initialization is complete unless dual-core
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support is not enabled in which case the cop_main function does not perform
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any kernel or thread initialization. It's just a trivial sleep loop. */
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#if NUM_CORES == 1
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ldr r4, =COP_CTRL
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mov r3, #WAKE
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str r3, [r4]
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#endif
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ldr pc, =main
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/* main() should never return */
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cop_init:
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#if NUM_CORES > 1
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/* Wait for CPU to go to sleep at the end of its kernel init */
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ldr r4, =CPU_STATUS
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1:
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ldr r3, [r4]
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tst r3, #CPUSLEEPING
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beq 1b
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#endif
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/* Set up stack for IRQ mode */
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msr cpsr_c, #0x92 /* IRQ disabled, FIQ enabled */
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ldr sp, =cop_irq_stack
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/* Set up stack for FIQ mode */
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msr cpsr_c, #0xd1 /* IRQ/FIQ disabled */
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ldr sp, =cop_fiq_stack
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/* Let svc, abort and undefined modes use irq stack */
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msr cpsr_c, #0xd3 /* IRQ/FIQ disabled */
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ldr sp, =cop_irq_stack
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msr cpsr_c, #0xd7 /* IRQ/FIQ disabled */
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ldr sp, =cop_irq_stack
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msr cpsr_c, #0xdb /* IRQ/FIQ disabled */
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ldr sp, =cop_irq_stack
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/* Switch to sys mode */
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msr cpsr_c, #0xdf
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/* Set up idle stack for COP and munge it with 0xdeadbeef */
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ldr sp, =cop_idlestackend
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ldr r2, =cop_idlestackbegin
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ldr r4, =0xdeadbeef
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2:
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cmp sp, r2
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strhi r4, [r2], #4
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bhi 2b
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/* Run cop_main() in apps/main.c */
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ldr pc, =cop_main
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/* Exception handlers. Will be copied to address 0 after memory remapping */
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.section .vectors,"aw"
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ldr pc, [pc, #24]
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ldr pc, [pc, #24]
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ldr pc, [pc, #24]
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ldr pc, [pc, #24]
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ldr pc, [pc, #24]
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ldr pc, [pc, #24]
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ldr pc, [pc, #24]
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ldr pc, [pc, #24]
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/* Exception vectors */
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.global vectors
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vectors:
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.word start
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.word undef_instr_handler
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.word software_int_handler
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.word prefetch_abort_handler
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.word data_abort_handler
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.word reserved_handler
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.word irq_handler
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.word fiq_handler
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.text
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/* All illegal exceptions call into UIE with exception address as first
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parameter. This is calculated differently depending on which exception
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we're in. Second parameter is exception number, used for a string lookup
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in UIE.
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*/
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undef_instr_handler:
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sub r0, lr, #4
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mov r1, #0
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b UIE
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/* We run sys mode most of the time, and should never see a software
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exception being thrown. Make it illegal and call UIE.
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*/
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software_int_handler:
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reserved_handler:
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sub r0, lr, #4
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mov r1, #4
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b UIE
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prefetch_abort_handler:
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sub r0, lr, #4
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mov r1, #1
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b UIE
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#if defined(HAVE_BOOTDATA) && !defined(BOOTLOADER)
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/* boot data structure */
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put_boot_data_here
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#endif
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/* Align stacks to cache line boundary */
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.balign 32
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/* 256 words of IRQ stack */
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.space 256*4
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irq_stack:
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/* 256 words of COP IRQ stack */
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.space 256*4
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cop_irq_stack:
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/* 256 words of FIQ stack */
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.space 256*4
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fiq_stack:
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/* We'll need this soon - just reserve the symbol */
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#if 0
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/* 256 words of COP FIQ stack */
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.space 256*4
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#endif
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cop_fiq_stack:
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