259 lines
6.0 KiB
ArmAsm
259 lines
6.0 KiB
ArmAsm
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id: $
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*
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* Copyright (C) 2011 by Tomasz Moń
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include "config.h"
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#include "cpu.h"
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/* Macro for reading a register */
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.macro mrh register
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ldr r1, =\register
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ldrh r0, [r1]
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.endm
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/* Macro for writing a register */
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.macro mwh register, value
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ldr r0, =\value
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ldr r1, =\register
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strh r0, [r1]
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.endm
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/* This version uses a mov to save on the literal pool size. Otherwise it is
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* functionally equivalent.
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*/
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.macro mwhm register, value
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mov r0, #\value
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ldr r1, =\register
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strh r0, [r1]
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.endm
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/*
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* _init_board:
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* This function initializes the specific board this SoC is on.
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*/
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.section .init, "ax"
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.code 32
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.align 0x04
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.global _init_board
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.type _init_board, %function
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_init_board:
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/* Setup the EMIF interface timings */
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/* FLASH interface:
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* These are based on the OF setup
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*/
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/* IO_EMIF_CS0CTRL1 and
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* IO_EMIF_CS0CTRL2
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*/
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mwh 0x30A00, 0x889A
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mwh 0x30A02, 0x1110
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mwhm 0x30A04, 0
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mwh 0x30A06, 0x1415
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mwh 0x30A08, 0x1109
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mwh 0x30A0A, 0x1220
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mwh 0x30A0C, 0x1104
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mwh 0x30A0E, 0x0222
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/* IO_EMIF_CS3CTRL1 and
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* IO_EMIF_CS3CTRL2
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*/
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mwh 0x30A10, 0x8899
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mwh 0x30A12, 0x5110
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/* USB interface */
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/* IO_EMIF_CS4CTRL1 and
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* IO_EMIF_CS4CTRL2
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*/
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mwh 0x30A14, 0x77DF
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mwh 0x30A16, 0x7740
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/* IO_EMIF_BUSCTRL */
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mwhm 0x30A18, 0
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mwhm 0x30A1A, 0
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mwhm 0x30A1C, 0
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mwhm 0x30A1E, 0
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_clock_setup:
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/* Clock initialization */
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/* Disable peripheral clocks */
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mwhm 0x3089A, 0
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mwhm 0x3089C, 0
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/* IO_CLK_BYP: Bypass the PLLs for the following changes */
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mwh 0x30894, 0x1111
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/*
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* IO_CLK_PLLA: 27 MHz * 11 / 1 = 297 MHz
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* IO_CLK_PLLB: 27 MHz
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*/
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mwh 0x30880, 0x10A0
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mwhm 0x30882, 0x1000
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/* IO_CLK_SEL0: Timer 0 and 1, UART 0 and 1 from PLLIN (27 MHz) */
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mwh 0x30884, 0x0066
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/* IO_CLK_SEL1: VENC from PLLA, OSD clock = VENC clock / 2 */
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mwhm 0x30886, 0x0003
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/* IO_CLK_SEL2: ARM, AXL, SDRAM and DSP are from PLLA */
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mwh 0x30888, 0
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/* IO_CLK_DIV0: Set the fast clock speed for the ARM/AHB
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* ARM = PLLA / 2 = 148.5 MHz
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* AHB = ARM / 2 = 74.25 MHz
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*/
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mwh 0x3088A, 0x0101
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/* IO_CLK_DIV1: Accelerator, SDRAM
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* AXL = PLLA / 2 = 148.5 MHz
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* SDRAM = PLLA / 3 = 99 MHz
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*/
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mwh 0x3088C, 0x0102
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/* IO_CLK_DIV2: DSP, MS Clock
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* OF must be booted with this value
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* DSP = PLLA / 3 = 99 MHz
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* MS = PLLA / 1 = 297 MHz
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*/
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mwhm 0x3088E, 0x0200
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/* PLLA &= ~0x1000 (BIC #0x1000) */
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mrh 0x30880
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bic r0, r0, #0x1000
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strh r0, [r1]
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/* Wait for PLLs to lock before feeding them to the downstream devices */
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_plla_wait:
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mrh 0x30880
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bic r0, r0, #0x7F
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tst r0, r0
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beq _plla_wait
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/* IO_CLK_BYP: Enable PLL feeds */
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mwhm 0x30894, 0x0
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/* IO_CLK_MOD0
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* Enable clocks:
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* ARM, Bus Controller, AHB, ARM internal memory, EMIF, SDRAM
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* Disable clocks:
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* ETM, E2ICE, INTC, EXTHOST, DSP, HPIB
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*/
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mwh 0x30898, 0x01A7
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/* IO_CLK_MOD2: Enable GIO and SIF1 clocks */
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mwhm 0x3089C, 0x0420
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/* Setup the SDRAM range on the AHB bus */
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/* SDRAMSA */
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mov r0, #0x60000
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mov r1, #0x1000000
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str r1, [r0, #0xF00]
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/* SDRAMEA: 64MB */
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mov r1, #0x5000000
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str r1, [r0, #0xF04]
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/* SDRC_REFCTL */
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mwh 0x309A8, 0
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ldr r0, =0x309A6
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mov r2, #0x1380
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orr r1, r2, #2
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strh r1, [r0]
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orr r1, r2, #4
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strh r1, [r0]
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strh r1, [r0]
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strh r1, [r0]
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strh r1, [r0]
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strh r1, [r0]
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strh r1, [r0]
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strh r1, [r0]
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strh r1, [r0]
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orr r1, r2, #1
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strh r1, [r0]
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strh r2, [r0]
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strh r2, [r0]
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mwhm 0x309A8, 0x0140
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/* IMGBUF SDRAM priority bit 2 set */
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mwhm 0x309BE, 0x4
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/* SDRAM refresh priority bit 1 set */
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mwhm 0x309BC, 0x2
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/* Use defined priority bits */
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ldr r0, =0x309C4
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ldr r1, [r0]
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orr r1, r1, #1
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strh r1, [r0]
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ldr r0, =0x309A6
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mov r1, #0x1380
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strh r1, [r0]
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bic r1, r1, #0x80
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strh r1, [r0]
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orr r1, r1, #0x40
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strh r1, [r0]
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/* Enable auto refresh with interval (64 + 1) * 8 SDRAM clocks */
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mwhm 0x309A8, 0x0140
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/* Go through the GPIO initialization */
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/* Warning: setting some of the functions wrong will make OF unable
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to boot (freeze during startup) */
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/* IO_GIO_FSEL0: Set up the GPIO pin functions 0-16 */
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mwhm 0x305A4, 0xC000
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/* IO_GIO_FSEL1: 17-24 */
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mwh 0x305A6, 0xAAAA
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/* IO_GIO_FSEL2: 18-32 */
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mwh 0x305A8, 0xA80A
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/* IO_GIO_FSEL3: 33-40 */
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mwh 0x305AA, 0x1007
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/* IO_GIO_DIR0 */
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mwh 0x30580, 0xFF77
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/* IO_GIO_DIR1 */
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mwh 0x30582, 0xEFFE
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/* IO_GIO_DIR2 */
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mwh 0x30584, 0x01FD
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/* IO_GIO_INV0 */
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mwh 0x30586, 0x0000
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/* IO_GIO_INV1 */
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mwh 0x30588, 0x0000
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/* IO_GIO_INV2 */
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mwh 0x3058A, 0x0000
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bx lr
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.ltorg
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.size _init_board, .-_init_board
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