862 lines
21 KiB
C
862 lines
21 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2008 by Maurus Cuelenaere
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include "config.h"
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/*#define LOGF_ENABLE*/
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#include "logf.h"
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#include "system.h"
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#include "usb_ch9.h"
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#include "usb_drv.h"
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#include "usb_core.h"
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#include "jz4740.h"
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#include "thread.h"
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/*
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The Jz4740 USB controller is called MUSBHSFC in the datasheet.
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It also seems to be a more generic controller, with support for
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up to 15 endpoints (the Jz4740 only has 5).
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*/
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#define EP_BUF_LEFT(ep) ((ep)->length - (ep)->sent)
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#define EP_PTR(ep) ((void*)((unsigned int)(ep)->buf + (ep)->sent))
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#define EP_NUMBER(ep) (((int)(ep) - (int)&endpoints[0])/sizeof(struct usb_endpoint))
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#define EP_NUMBER2(ep) (EP_NUMBER((ep))/2)
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#define TOTAL_EP() (sizeof(endpoints)/sizeof(struct usb_endpoint))
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#define EP_IS_IN(ep) (EP_NUMBER((ep))%2)
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enum ep_type
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{
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ep_control,
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ep_bulk,
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ep_interrupt,
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ep_isochronous
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};
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struct usb_endpoint
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{
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void *buf;
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size_t length;
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union
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{
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size_t sent;
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size_t received;
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};
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bool busy;
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const enum ep_type type;
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const bool use_dma;
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const long fifo_addr;
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unsigned short fifo_size;
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bool wait;
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struct semaphore complete;
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};
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static unsigned char ep0_rx_buf[64];
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static struct usb_endpoint endpoints[] =
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{
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{ .type = ep_control, .fifo_addr = USB_FIFO_EP0, .fifo_size = 64 },
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{ .type = ep_control, .fifo_addr = USB_FIFO_EP0, .buf = &ep0_rx_buf },
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{ .type = ep_bulk, .fifo_addr = USB_FIFO_EP1, .fifo_size = 512 },
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{ .type = ep_bulk, .fifo_addr = USB_FIFO_EP1, .fifo_size = 512 },
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{ .type = ep_interrupt, .fifo_addr = USB_FIFO_EP2, .fifo_size = 64 },
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};
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static inline void select_endpoint(int ep)
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{
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REG_USB_REG_INDEX = ep;
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}
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static void readFIFO(struct usb_endpoint *ep, unsigned int size)
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{
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logf("%s(EP%d, %d)", __func__, EP_NUMBER2(ep), size);
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register unsigned char *ptr = (unsigned char*)EP_PTR(ep);
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register unsigned int *ptr32 = (unsigned int*)ptr;
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register unsigned int s = size >> 2;
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register unsigned int x;
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if(size > 0)
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{
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if( ((unsigned int)ptr & 3) == 0 )
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{
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while(s--)
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*ptr32++ = REG32(ep->fifo_addr);
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ptr = (unsigned char*)ptr32;
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}
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else
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{
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while(s--)
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{
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x = REG32(ep->fifo_addr);
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*ptr++ = x & 0xFF; x >>= 8;
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*ptr++ = x & 0xFF; x >>= 8;
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*ptr++ = x & 0xFF; x >>= 8;
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*ptr++ = x;
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}
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}
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s = size & 3;
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while(s--)
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*ptr++ = REG8(ep->fifo_addr);
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}
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}
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static void writeFIFO(struct usb_endpoint *ep, size_t size)
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{
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logf("%s(EP%d, %d)", __func__, EP_NUMBER2(ep), size);
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register unsigned int *d32 = (unsigned int *)EP_PTR(ep);
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register size_t s = size >> 2;
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if(size > 0)
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{
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while (s--)
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REG32(ep->fifo_addr) = *d32++;
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if( (s = size & 3) )
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{
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register unsigned char *d8 = (unsigned char *)d32;
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while (s--)
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REG8(ep->fifo_addr) = *d8++;
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}
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}
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}
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static void flushFIFO(struct usb_endpoint *ep)
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{
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logf("%s(%d)", __func__, EP_NUMBER(ep));
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switch (ep->type)
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{
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case ep_control:
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break;
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case ep_bulk:
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case ep_interrupt:
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case ep_isochronous:
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if(EP_IS_IN(ep))
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REG_USB_REG_INCSR |= (USB_INCSR_FF | USB_INCSR_CDT);
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else
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REG_USB_REG_OUTCSR |= (USB_OUTCSR_FF | USB_OUTCSR_CDT);
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break;
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}
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}
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static inline void ep_transfer_completed(struct usb_endpoint* ep)
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{
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ep->sent = 0;
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ep->length = 0;
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ep->buf = NULL;
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ep->busy = false;
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if(ep->wait)
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semaphore_release(&ep->complete);
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}
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static void EP0_send(void)
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{
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struct usb_endpoint* ep = &endpoints[0];
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unsigned int length;
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unsigned char csr0;
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select_endpoint(0);
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csr0 = REG_USB_REG_CSR0;
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if(ep->sent == 0)
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length = MIN(ep->length, ep->fifo_size);
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else
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length = MIN(EP_BUF_LEFT(ep), ep->fifo_size);
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writeFIFO(ep, length);
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ep->sent += length;
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if(ep->sent >= ep->length)
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{
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REG_USB_REG_CSR0 = (csr0 | USB_CSR0_INPKTRDY | USB_CSR0_DATAEND); /* Set data end! */
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usb_core_transfer_complete(0, USB_DIR_IN, 0, ep->sent);
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ep_transfer_completed(ep);
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}
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else
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REG_USB_REG_CSR0 = (csr0 | USB_CSR0_INPKTRDY);
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}
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static void EP0_handler(void)
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{
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logf("%s()", __func__);
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unsigned char csr0;
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struct usb_endpoint *ep_send = &endpoints[0];
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struct usb_endpoint *ep_recv = &endpoints[1];
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/* Read CSR0 */
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select_endpoint(0);
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csr0 = REG_USB_REG_CSR0;
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/* Check for SentStall:
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This bit is set when a STALL handshake is transmitted. The CPU should clear this bit.
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*/
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if(csr0 & USB_CSR0_SENTSTALL)
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{
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REG_USB_REG_CSR0 = csr0 & ~USB_CSR0_SENTSTALL;
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return;
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}
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/* Check for SetupEnd:
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This bit will be set when a control transaction ends before the DataEnd bit has been set.
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An interrupt will be generated and the FIFO flushed at this time.
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The bit is cleared by the CPU writing a 1 to the ServicedSetupEnd bit.
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*/
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if(csr0 & USB_CSR0_SETUPEND)
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{
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REG_USB_REG_CSR0 = csr0 | USB_CSR0_SVDSETUPEND;
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return;
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}
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/* Call relevant routines for endpoint 0 state */
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if(ep_send->busy)
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EP0_send();
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else if(csr0 & USB_CSR0_OUTPKTRDY) /* There is a packet in the fifo */
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{
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readFIFO(ep_recv, REG_USB_REG_COUNT0);
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REG_USB_REG_CSR0 = csr0 | USB_CSR0_SVDOUTPKTRDY; /* clear OUTPKTRDY bit */
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usb_core_legacy_control_request((struct usb_ctrlrequest*)ep_recv->buf);
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}
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}
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static void EPIN_handler(unsigned int endpoint)
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{
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struct usb_endpoint* ep = &endpoints[endpoint*2];
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unsigned int length, csr;
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select_endpoint(endpoint);
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csr = REG_USB_REG_INCSR;
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logf("%s(%d): 0x%x", __func__, endpoint, csr);
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if(!ep->busy)
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{
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logf("Entered EPIN handler without work!");
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return;
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}
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if(csr & USB_INCSR_SENTSTALL)
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{
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REG_USB_REG_INCSR = csr & ~USB_INCSR_SENTSTALL;
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return;
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}
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if(ep->use_dma)
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return;
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if(csr & USB_INCSR_FFNOTEMPT)
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{
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logf("FIFO is not empty! 0x%x", csr);
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return;
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}
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logf("EP%d: %d -> %d", endpoint, ep->sent, ep->length);
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if(ep->sent == 0)
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length = MIN(ep->length, ep->fifo_size);
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else
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length = MIN(EP_BUF_LEFT(ep), ep->fifo_size);
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writeFIFO(ep, length);
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REG_USB_REG_INCSR = csr | USB_INCSR_INPKTRDY;
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ep->sent += length;
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if(ep->sent >= ep->length)
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{
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usb_core_transfer_complete(endpoint, USB_DIR_IN, 0, ep->sent);
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ep_transfer_completed(ep);
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logf("sent complete");
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}
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}
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static void EPOUT_handler(unsigned int endpoint)
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{
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struct usb_endpoint* ep = &endpoints[endpoint*2+1];
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unsigned int size, csr;
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if(!ep->busy)
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{
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logf("Entered EPOUT handler without work!");
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return;
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}
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select_endpoint(endpoint);
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while((csr = REG_USB_REG_OUTCSR) & (USB_OUTCSR_SENTSTALL|USB_OUTCSR_OUTPKTRDY))
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{
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logf("%s(%d): 0x%x", __func__, endpoint, csr);
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if(csr & USB_OUTCSR_SENTSTALL)
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{
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logf("stall sent, flushing fifo..");
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flushFIFO(ep);
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REG_USB_REG_OUTCSR = csr & ~USB_OUTCSR_SENTSTALL;
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return;
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}
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if(ep->use_dma)
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return;
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if(csr & USB_OUTCSR_OUTPKTRDY) /* There is a packet in the fifo */
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{
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size = REG_USB_REG_OUTCOUNT;
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readFIFO(ep, size);
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ep->received += size;
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/*if(csr & USB_OUTCSR_FFFULL)
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csr &= ~USB_OUTCSR_FFFULL;*/
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REG_USB_REG_OUTCSR = csr & ~USB_OUTCSR_OUTPKTRDY;
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logf("received: %d max length: %d", ep->received, ep->length);
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if(size < ep->fifo_size || ep->received >= ep->length)
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{
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usb_core_transfer_complete(endpoint, USB_DIR_OUT, 0, ep->received);
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ep_transfer_completed(ep);
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logf("receive transfer_complete");
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}
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}
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}
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}
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static void EPDMA_handler(int number)
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{
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int endpoint = -1;
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unsigned int size = 0;
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if(number == USB_INTR_DMA_BULKIN)
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endpoint = (REG_USB_REG_CNTL1 >> 4) & 0xF;
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else if(number == USB_INTR_DMA_BULKOUT)
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endpoint = (REG_USB_REG_CNTL2 >> 4) & 0xF;
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struct usb_endpoint* ep = &endpoints[endpoint];
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logf("DMA_BULK%d %d", number, endpoint);
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if(number == USB_INTR_DMA_BULKIN)
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size = (unsigned int)ep->buf - REG_USB_REG_ADDR1;
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else if(number == USB_INTR_DMA_BULKOUT)
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size = (unsigned int)ep->buf - REG_USB_REG_ADDR2;
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if(number == USB_INTR_DMA_BULKOUT)
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{
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/* Disable DMA */
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REG_USB_REG_CNTL2 = 0;
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select_endpoint(endpoint);
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/* Read out last packet manually */
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unsigned int lpack_size = REG_USB_REG_OUTCOUNT;
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if(lpack_size > 0)
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{
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ep->buf += ep->length - lpack_size;
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readFIFO(ep, lpack_size);
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REG_USB_REG_OUTCSR &= ~USB_OUTCSR_OUTPKTRDY;
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}
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}
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else if(number == USB_INTR_DMA_BULKIN && size % ep->fifo_size)
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{
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/* If the last packet is less than MAXP, set INPKTRDY manually */
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REG_USB_REG_INCSR |= USB_INCSR_INPKTRDY;
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}
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usb_core_transfer_complete(endpoint, EP_IS_IN(ep) ? USB_DIR_IN : USB_DIR_OUT,
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0, ep->length);
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ep_transfer_completed(ep);
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}
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static void setup_endpoint(struct usb_endpoint *ep)
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{
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int csr, csrh;
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select_endpoint(EP_NUMBER2(ep));
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ep->busy = false;
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ep->wait = false;
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ep->sent = 0;
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ep->length = 0;
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if(ep->type == ep_bulk)
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{
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if(REG_USB_REG_POWER & USB_POWER_HSMODE)
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ep->fifo_size = 512;
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else
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ep->fifo_size = 64;
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}
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if(EP_IS_IN(ep))
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{
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csr = (USB_INCSR_FF | USB_INCSR_CDT);
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csrh = USB_INCSRH_MODE;
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if(ep->use_dma)
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csrh |= (USB_INCSRH_DMAREQENAB | USB_INCSRH_AUTOSET | USB_INCSRH_DMAREQMODE);
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if(ep->type == ep_interrupt)
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csrh |= USB_INCSRH_FRCDATATOG;
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REG_USB_REG_INMAXP = ep->fifo_size;
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REG_USB_REG_INCSR = csr;
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REG_USB_REG_INCSRH = csrh;
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REG_USB_REG_INTRINE |= USB_INTR_EP(EP_NUMBER2(ep));
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}
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else
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{
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csr = (USB_OUTCSR_FF | USB_OUTCSR_CDT);
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csrh = 0;
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if(ep->type == ep_interrupt)
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csrh |= USB_OUTCSRH_DNYT;
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if(ep->use_dma)
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csrh |= (USB_OUTCSRH_DMAREQENAB | USB_OUTCSRH_AUTOCLR | USB_OUTCSRH_DMAREQMODE);
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REG_USB_REG_OUTMAXP = ep->fifo_size;
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REG_USB_REG_OUTCSR = csr;
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REG_USB_REG_OUTCSRH = csrh;
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REG_USB_REG_INTROUTE |= USB_INTR_EP(EP_NUMBER2(ep));
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}
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}
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static void udc_reset(void)
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{
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/* From the datasheet:
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When a reset condition is detected on the USB, the controller performs the following actions:
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* Sets FAddr to 0.
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* Sets Index to 0.
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* Flushes all endpoint FIFOs.
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* Clears all control/status registers.
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* Enables all endpoint interrupts.
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* Generates a Reset interrupt.
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*/
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logf("%s()", __func__);
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unsigned int i;
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/* Disable interrupts */
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REG_USB_REG_INTRINE = 0;
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REG_USB_REG_INTROUTE = 0;
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REG_USB_REG_INTRUSBE = 0;
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/* Disable DMA */
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REG_USB_REG_CNTL1 = 0;
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REG_USB_REG_CNTL2 = 0;
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/* High speed, softconnect and suspend/resume */
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REG_USB_REG_POWER = (USB_POWER_SOFTCONN | USB_POWER_HSENAB | USB_POWER_SUSPENDM);
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/* Reset EP0 */
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select_endpoint(0);
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REG_USB_REG_CSR0 = (USB_CSR0_SVDOUTPKTRDY | USB_CSR0_SVDSETUPEND);
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/* Reset other endpoints */
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for(i=2; i<TOTAL_EP(); i++)
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setup_endpoint(&endpoints[i]);
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/* Enable interrupts */
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REG_USB_REG_INTRINE |= USB_INTR_EP0;
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REG_USB_REG_INTRUSBE |= USB_INTR_RESET;
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usb_core_bus_reset();
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}
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/* Interrupt handler */
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void UDC(void)
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{
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/* Read interrupt registers */
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unsigned char intrUSB = REG_USB_REG_INTRUSB & 0x07; /* Mask SOF */
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unsigned short intrIn = REG_USB_REG_INTRIN;
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unsigned short intrOut = REG_USB_REG_INTROUT;
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unsigned char intrDMA = REG_USB_REG_INTR;
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logf("%x %x %x %x", intrUSB, intrIn, intrOut, intrDMA);
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/* EPIN & EPOUT are all handled in DMA */
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if(intrIn & USB_INTR_EP0)
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EP0_handler();
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if(intrIn & USB_INTR_INEP1)
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EPIN_handler(1);
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if(intrIn & USB_INTR_INEP2)
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EPIN_handler(2);
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if(intrOut & USB_INTR_OUTEP1)
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EPOUT_handler(1);
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if(intrOut & USB_INTR_OUTEP2)
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EPOUT_handler(2);
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if(intrUSB & USB_INTR_RESET)
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udc_reset();
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if(intrUSB & USB_INTR_SUSPEND)
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{
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logf("USB suspend");
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}
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if(intrUSB & USB_INTR_RESUME)
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{
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logf("USB resume");
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}
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if(intrDMA & USB_INTR_DMA_BULKIN)
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EPDMA_handler(USB_INTR_DMA_BULKIN);
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|
if(intrDMA & USB_INTR_DMA_BULKOUT)
|
|
EPDMA_handler(USB_INTR_DMA_BULKOUT);
|
|
}
|
|
|
|
bool usb_drv_stalled(int endpoint, bool in)
|
|
{
|
|
endpoint &= 0x7F;
|
|
|
|
logf("%s(%d, %s)", __func__, endpoint, in?"IN":"OUT");
|
|
|
|
select_endpoint(endpoint);
|
|
|
|
if(endpoint == EP_CONTROL)
|
|
return (REG_USB_REG_CSR0 & USB_CSR0_SENDSTALL) != 0;
|
|
else
|
|
{
|
|
if(in)
|
|
return (REG_USB_REG_INCSR & USB_INCSR_SENDSTALL) != 0;
|
|
else
|
|
return (REG_USB_REG_OUTCSR & USB_OUTCSR_SENDSTALL) != 0;
|
|
}
|
|
}
|
|
|
|
void usb_drv_stall(int endpoint, bool stall, bool in)
|
|
{
|
|
endpoint &= 0x7F;
|
|
|
|
logf("%s(%d,%s,%s)", __func__, endpoint, stall?"Y":"N", in?"IN":"OUT");
|
|
|
|
select_endpoint(endpoint);
|
|
|
|
if(endpoint == EP_CONTROL)
|
|
{
|
|
if(stall)
|
|
REG_USB_REG_CSR0 |= USB_CSR0_SENDSTALL;
|
|
else
|
|
REG_USB_REG_CSR0 &= ~USB_CSR0_SENDSTALL;
|
|
}
|
|
else
|
|
{
|
|
if(in)
|
|
{
|
|
if(stall)
|
|
REG_USB_REG_INCSR |= USB_INCSR_SENDSTALL;
|
|
else
|
|
REG_USB_REG_INCSR = (REG_USB_REG_INCSR & ~USB_INCSR_SENDSTALL) | USB_INCSR_CDT;
|
|
}
|
|
else
|
|
{
|
|
if(stall)
|
|
REG_USB_REG_OUTCSR |= USB_OUTCSR_SENDSTALL;
|
|
else
|
|
REG_USB_REG_OUTCSR = (REG_USB_REG_OUTCSR & ~USB_OUTCSR_SENDSTALL) | USB_OUTCSR_CDT;
|
|
}
|
|
}
|
|
}
|
|
|
|
#define GPIO_UDC_DETE (32 * 3 + 28) /* A18 = ADP_CHK */
|
|
#define IRQ_GPIO_UDC_DETE (IRQ_GPIO_0 + GPIO_UDC_DETE)
|
|
#ifndef ONDA_VX767
|
|
# define USB_GPIO_IRQ GPIO124
|
|
#endif
|
|
|
|
int usb_detect(void)
|
|
{
|
|
return (__gpio_get_pin(GPIO_UDC_DETE) == 1)
|
|
? USB_INSERTED : USB_EXTRACTED;
|
|
}
|
|
|
|
void usb_init_device(void)
|
|
{
|
|
#ifdef ONDA_VX767
|
|
REG_GPIO_PXFUNS(3) = 0x10000000;
|
|
REG_GPIO_PXSELS(3) = 0x10000000;
|
|
REG_GPIO_PXPES(3) = 0x10000000;
|
|
__gpio_as_input(GPIO_UDC_DETE);
|
|
#else
|
|
REG_GPIO_PXPES(3) = 0x10000000;
|
|
__gpio_as_irq_rise_edge(GPIO_UDC_DETE);
|
|
#endif
|
|
|
|
#ifdef USB_GPIO_IRQ
|
|
system_enable_irq(IRQ_GPIO_UDC_DETE);
|
|
#endif
|
|
system_enable_irq(IRQ_UDC);
|
|
|
|
for(unsigned i=0; i<TOTAL_EP(); i++)
|
|
semaphore_init(&endpoints[i].complete, 1, 0);
|
|
}
|
|
|
|
#ifdef USB_GPIO_IRQ
|
|
static unsigned long last_tick;
|
|
void USB_GPIO_IRQ(void)
|
|
{
|
|
/* Prevent enabled-disabled bouncing */
|
|
if(current_tick - last_tick > HZ/16)
|
|
{
|
|
usb_status_event(usb_detect());
|
|
last_tick = current_tick;
|
|
}
|
|
}
|
|
#endif
|
|
|
|
void usb_enable(bool on)
|
|
{
|
|
if(on)
|
|
usb_core_init();
|
|
else
|
|
usb_core_exit();
|
|
}
|
|
|
|
void usb_attach(void)
|
|
{
|
|
usb_enable(true);
|
|
}
|
|
|
|
void usb_drv_init(void)
|
|
{
|
|
logf("%s()", __func__);
|
|
|
|
/* Set this bit to allow the UDC entering low-power mode when
|
|
* there are no actions on the USB bus.
|
|
* UDC still works during this bit was set.
|
|
*/
|
|
//__cpm_stop_udc();
|
|
__cpm_start_udc();
|
|
|
|
/* Enable the USB PHY */
|
|
REG_CPM_SCR |= CPM_SCR_USBPHY_ENABLE;
|
|
|
|
/* Dis- and reconnect from USB */
|
|
REG_USB_REG_POWER &= ~USB_POWER_SOFTCONN;
|
|
REG_USB_REG_POWER |= USB_POWER_SOFTCONN;
|
|
|
|
udc_reset();
|
|
}
|
|
|
|
void usb_drv_exit(void)
|
|
{
|
|
logf("%s()", __func__);
|
|
|
|
/* Disable interrupts */
|
|
REG_USB_REG_INTRINE = 0;
|
|
REG_USB_REG_INTROUTE = 0;
|
|
REG_USB_REG_INTRUSBE = 0;
|
|
|
|
/* Disable DMA */
|
|
REG_USB_REG_CNTL1 = 0;
|
|
REG_USB_REG_CNTL2 = 0;
|
|
|
|
/* Disconnect from USB */
|
|
REG_USB_REG_POWER &= ~USB_POWER_SOFTCONN;
|
|
|
|
/* Disable the USB PHY */
|
|
REG_CPM_SCR &= ~CPM_SCR_USBPHY_ENABLE;
|
|
|
|
__cpm_stop_udc();
|
|
}
|
|
|
|
void usb_drv_set_address(int address)
|
|
{
|
|
logf("%s(%d)", __func__, address);
|
|
|
|
REG_USB_REG_FADDR = address;
|
|
}
|
|
|
|
static void usb_drv_send_internal(struct usb_endpoint* ep, void* ptr, int length, bool blocking)
|
|
{
|
|
if(ep->type == ep_control && ptr == NULL && length == 0)
|
|
return; /* ACK request, handled in the ISR */
|
|
|
|
int flags = disable_irq_save();
|
|
|
|
ep->buf = ptr;
|
|
ep->sent = 0;
|
|
ep->length = length;
|
|
ep->busy = true;
|
|
if(blocking)
|
|
ep->wait = true;
|
|
|
|
if(ep->type == ep_control)
|
|
{
|
|
EP0_send();
|
|
}
|
|
else
|
|
{
|
|
if(ep->use_dma)
|
|
{
|
|
commit_discard_dcache_range(ptr, length);
|
|
REG_USB_REG_ADDR1 = PHYSADDR((unsigned long)ptr);
|
|
REG_USB_REG_COUNT1 = length;
|
|
REG_USB_REG_CNTL1 = (USB_CNTL_INTR_EN | USB_CNTL_MODE_1 |
|
|
USB_CNTL_DIR_IN | USB_CNTL_ENA |
|
|
USB_CNTL_EP(EP_NUMBER2(ep)) | USB_CNTL_BURST_16);
|
|
}
|
|
else
|
|
EPIN_handler(EP_NUMBER2(ep));
|
|
}
|
|
|
|
restore_irq(flags);
|
|
|
|
if(blocking)
|
|
{
|
|
semaphore_wait(&ep->complete, TIMEOUT_BLOCK);
|
|
ep->wait = false;
|
|
}
|
|
}
|
|
|
|
int usb_drv_send_nonblocking(int endpoint, void* ptr, int length)
|
|
{
|
|
logf("%s(%d, 0x%x, %d)", __func__, endpoint, (int)ptr, length);
|
|
|
|
usb_drv_send_internal(&endpoints[(endpoint & 0x7F)*2], ptr, length, false);
|
|
|
|
return 0;
|
|
}
|
|
|
|
int usb_drv_send(int endpoint, void* ptr, int length)
|
|
{
|
|
logf("%s(%d, 0x%x, %d)", __func__, endpoint, (int)ptr, length);
|
|
|
|
usb_drv_send_internal(&endpoints[(endpoint & 0x7F)*2], ptr, length, true);
|
|
|
|
return 0;
|
|
}
|
|
|
|
int usb_drv_recv_nonblocking(int endpoint, void* ptr, int length)
|
|
{
|
|
int flags;
|
|
struct usb_endpoint *ep;
|
|
endpoint &= 0x7F;
|
|
|
|
logf("%s(%d, 0x%x, %d)", __func__, endpoint, (int)ptr, length);
|
|
|
|
if(endpoint == EP_CONTROL)
|
|
return 0; /* all EP0 OUT transactions are handled within the ISR */
|
|
else
|
|
{
|
|
flags = disable_irq_save();
|
|
ep = &endpoints[endpoint*2+1];
|
|
|
|
ep->buf = ptr;
|
|
ep->received = 0;
|
|
ep->length = length;
|
|
ep->busy = true;
|
|
if(ep->use_dma)
|
|
{
|
|
discard_dcache_range(ptr, length);
|
|
REG_USB_REG_ADDR2 = PHYSADDR((unsigned long)ptr);
|
|
REG_USB_REG_COUNT2 = length;
|
|
REG_USB_REG_CNTL2 = (USB_CNTL_INTR_EN | USB_CNTL_MODE_1 |
|
|
USB_CNTL_ENA | USB_CNTL_EP(endpoint) |
|
|
USB_CNTL_BURST_16);
|
|
}
|
|
else
|
|
EPOUT_handler(endpoint);
|
|
|
|
restore_irq(flags);
|
|
return 0;
|
|
}
|
|
}
|
|
|
|
void usb_drv_set_test_mode(int mode)
|
|
{
|
|
logf("%s(%d)", __func__, mode);
|
|
|
|
switch(mode)
|
|
{
|
|
case 0:
|
|
REG_USB_REG_TESTMODE &= ~USB_TEST_ALL;
|
|
break;
|
|
case 1:
|
|
REG_USB_REG_TESTMODE |= USB_TEST_J;
|
|
break;
|
|
case 2:
|
|
REG_USB_REG_TESTMODE |= USB_TEST_K;
|
|
break;
|
|
case 3:
|
|
REG_USB_REG_TESTMODE |= USB_TEST_SE0NAK;
|
|
break;
|
|
case 4:
|
|
REG_USB_REG_TESTMODE |= USB_TEST_PACKET;
|
|
break;
|
|
}
|
|
}
|
|
|
|
int usb_drv_port_speed(void)
|
|
{
|
|
return (REG_USB_REG_POWER & USB_POWER_HSMODE) ? 1 : 0;
|
|
}
|
|
|
|
void usb_drv_cancel_all_transfers(void)
|
|
{
|
|
logf("%s()", __func__);
|
|
|
|
unsigned int i, flags;
|
|
flags = disable_irq_save();
|
|
|
|
for(i=0; i<TOTAL_EP(); i++)
|
|
{
|
|
if(i != 1) /* ep0 out needs special handling */
|
|
endpoints[i].buf = NULL;
|
|
|
|
endpoints[i].sent = 0;
|
|
endpoints[i].length = 0;
|
|
|
|
select_endpoint(i/2);
|
|
flushFIFO(&endpoints[i]);
|
|
}
|
|
restore_irq(flags);
|
|
}
|
|
|
|
void usb_drv_release_endpoint(int ep)
|
|
{
|
|
(void)ep;
|
|
logf("%s(%d, %s)", __func__, (ep & 0x7F), (ep >> 7) ? "IN" : "OUT");
|
|
}
|
|
|
|
int usb_drv_request_endpoint(int type, int dir)
|
|
{
|
|
logf("%s(%d, %s)", __func__, type, (dir == USB_DIR_IN) ? "IN" : "OUT");
|
|
|
|
dir &= USB_ENDPOINT_DIR_MASK;
|
|
type &= USB_ENDPOINT_XFERTYPE_MASK;
|
|
|
|
/* There are only 3+2 endpoints, so hardcode this ... */
|
|
switch(type)
|
|
{
|
|
case USB_ENDPOINT_XFER_BULK:
|
|
if(dir == USB_DIR_IN)
|
|
return (1 | USB_DIR_IN);
|
|
else
|
|
return (1 | USB_DIR_OUT);
|
|
|
|
case USB_ENDPOINT_XFER_INT:
|
|
if(dir == USB_DIR_IN)
|
|
return (2 | USB_DIR_IN);
|
|
|
|
default:
|
|
return -1;
|
|
}
|
|
}
|