595 lines
17 KiB
C
595 lines
17 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Tuner "middleware" for Silicon Labs SI4700 chip
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*
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* Copyright (C) 2008 Nils Wallménius
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include "config.h"
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#include "system.h"
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#include <string.h>
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#include "kernel.h"
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#include "power.h"
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#include "tuner.h" /* tuner abstraction interface */
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#include "fmradio.h"
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#include "fmradio_i2c.h" /* physical interface driver */
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#include "rds.h"
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#if defined(SANSA_CLIP) || defined(SANSA_E200V2) || defined(SANSA_FUZE) || defined(SANSA_C200V2) \
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|| defined(SANSA_FUZEPLUS)
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/* some models use the internal 32 kHz oscillator which needs special attention
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during initialisation, power-up and power-down. */
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#define SI4700_USE_INTERNAL_OSCILLATOR
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#elif defined(TOSHIBA_GIGABEAT_S)
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/* gigabeat S uses the GPIO for stereo/mono detection */
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#define SI4700_USE_MO_ST_I
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#endif
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#define SEEK_THRESHOLD 0x16
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#define I2C_ADR 0x20
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/* define RSSI range */
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#define RSSI_MIN 0
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#define RSSI_MAX 70
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/** Registers and bits - "x" denotes Si4702/03 only (so they say) **/
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#define DEVICEID 0x0
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#define CHIPID 0x1
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#define POWERCFG 0x2
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#define CHANNEL 0x3
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#define SYSCONFIG1 0x4
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#define SYSCONFIG2 0x5
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#define SYSCONFIG3 0x6
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#define TEST1 0x7
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#define TEST2 0x8
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#define BOOTCONFIG 0x9
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#define STATUSRSSI 0xA
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#define READCHAN 0xB
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#define RDSA 0xC /* x */
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#define RDSB 0xD /* x */
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#define RDSC 0xE /* x */
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#define RDSD 0xF /* x */
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/* DEVICEID (0x0) */
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#define DEVICEID_PN (0xf << 12)
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/* 0x01 = Si4700/01 */
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/* 0x01 = Si4702/03 */
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#define DEVICEID_MFGID (0xfff << 0)
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/* always 0x242 */
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/* CHIPID (0x1) */
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#if 0
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/* Informational */
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/* Si4700/01 */
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#define CHIPID_REV (0x3f << 10)
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#define CHIPID_DEV (0x1 << 9)
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/* 0 before powerup */
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/* 0 after powerup = Si4700 */
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/* 1 after powerup = Si4701 */
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#define CHIPID_FIRMWARE (0xff << 0)
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/* Si4702/03 */
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#define CHIPID_REV (0x3f << 10)
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#define CHIPID_DEV (0xf << 6)
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/* 0000 before PU = Si4702 */
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/* 0001 after PU = Si4702 */
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/* 1000 before PU = Si4703 */
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/* 1001 after PU = Si4703 */
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#define CHIPID_FIRMWARE (0x3f << 0)
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#endif
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/* Indicates Si4701/2/3 after powerup */
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#define CHIPID_DEV_0 (0x1 << 9)
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/* POWERCFG (0x2) */
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#define POWERCFG_DSMUTE (0x1 << 15)
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#define POWERCFG_DMUTE (0x1 << 14)
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#define POWERCFG_MONO (0x1 << 13)
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#define POWERCFG_RDSM (0x1 << 11) /* x */
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#define POWERCFG_SKMODE (0x1 << 10)
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#define POWERCFG_SEEKUP (0x1 << 9)
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#define POWERCFG_SEEK (0x1 << 8)
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#define POWERCFG_DISABLE (0x1 << 6)
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#define POWERCFG_ENABLE (0x1 << 0)
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/* CHANNEL (0x3) */
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#define CHANNEL_TUNE (0x1 << 15)
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#define CHANNEL_CHAN (0x3ff << 0)
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#define CHANNEL_CHANw(x) ((x) & CHANNEL_CHAN)
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/* SYSCONFIG1 (0x4) */
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#define SYSCONFIG1_RDSIEN (0x1 << 15) /* x */
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#define SYSCONFIG1_STCIEN (0x1 << 14)
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#define SYSCONFIG1_RDS (0x1 << 12) /* x */
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#define SYSCONFIG1_DE (0x1 << 11)
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#define SYSCONFIG1_AGCD (0x1 << 10)
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#define SYSCONFIG1_BLNDADJ (0x3 << 6)
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#define SYSCONFIG1_BLNDADJ_31_39_RSSI (0x0 << 6)
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#define SYSCONFIG1_BLNDADJ_37_55_RSSI (0x1 << 6)
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#define SYSCONFIG1_BLNDADJ_19_37_RSSI (0x2 << 6)
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#define SYSCONFIG1_BLNDADJ_25_43_RSSI (0x3 << 6)
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#define SYSCONFIG1_GPIO3 (0x3 << 4)
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#define SYSCONFIG1_GPIO3_HI_Z (0x0 << 4)
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#define SYSCONFIG1_GPIO3_MO_ST_I (0x1 << 4)
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#define SYSCONFIG1_GPIO3_LOW (0x2 << 4)
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#define SYSCONFIG1_GPIO3_HI (0x3 << 4)
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#define SYSCONFIG1_GPIO2 (0x3 << 2)
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#define SYSCONFIG1_GPIO2_HI_Z (0x0 << 2)
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#define SYSCONFIG1_GPIO2_STC_RDS_I (0x1 << 2)
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#define SYSCONFIG1_GPIO2_LOW (0x2 << 2)
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#define SYSCONFIG1_GPIO2_HI (0x3 << 2)
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#define SYSCONFIG1_GPIO1 (0x3 << 0)
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#define SYSCONFIG1_GPIO1_HI_Z (0x0 << 0)
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#define SYSCONFIG1_GPIO1_LOW (0x2 << 0)
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#define SYSCONFIG1_GPIO1_HI (0x3 << 0)
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/* SYSCONFIG2 (0x5) */
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#define SYSCONFIG2_SEEKTH (0xff << 8)
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#define SYSCONFIG2_SEEKTHw(x) (((x) << 8) & SYSCONFIG2_SEEKTH)
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#define SYSCONFIG2_BAND (0x3 << 6)
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#define SYSCONFIG2_BANDw(x) (((x) << 6) & SYSCONFIG2_BAND)
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#define SYSCONFIG2_BANDr(x) (((x) & SYSCONFIG2_BAND) >> 6)
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#define SYSCONFIG2_BAND_875_1080 (0x0 << 6) /* tenth-megahertz */
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#define SYSCONFIG2_BAND_760_1080 (0x1 << 6)
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#define SYSCONFIG2_BAND_760_900 (0x2 << 6)
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#define SYSCONFIG2_SPACE (0x3 << 4)
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#define SYSCONFIG2_SPACEw(x) (((x) << 4) & SYSCONFIG2_SPACE)
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#define SYSCONFIG2_SPACEr(x) (((x) & SYSCONFIG2_SPACE) >> 4)
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#define SYSCONFIG2_SPACE_200KHZ (0x0 << 4)
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#define SYSCONFIG2_SPACE_100KHZ (0x1 << 4)
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#define SYSCONFIG2_SPACE_50KHZ (0x2 << 4)
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/* 4700/01 0000=mute,0001=-28dBFS..2dB steps..1111= +0dBFS */
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/* 4702/03: VOLEXT=0: 0000=mute,0001=-28dBFS..2dB steps..1111= +0dBFS */
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/* VOLEXT=1: 0000=mute,0001=-58dBFS..2dB steps..1111=-30dBFS */
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#define SYSCONFIG2_VOLUME (0xf << 0)
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#define SYSCONFIG2_VOLUMEw(x) ((x) & SYSCONFIG2_VOLUME)
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/* SYSCONFIG3 (0x6) */
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#define SYSCONFIG3_SMUTER (0x3 << 14)
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#define SYSCONFIG3_SMUTER_FASTEST (0x0 << 14)
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#define SYSCONFIG3_SMUTER_FAST (0x1 << 14)
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#define SYSCONFIG3_SMUTER_SLOW (0x2 << 14)
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#define SYSCONFIG3_SMUTER_SLOWEST (0x3 << 14)
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#define SYSCONFIG3_SMUTEA (0x3 << 12)
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#define SYSCONFIG3_SMUTEA_16DB (0x0 << 12)
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#define SYSCONFIG3_SMUTEA_14DB (0x1 << 12)
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#define SYSCONFIG3_SMUTEA_12DB (0x2 << 12)
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#define SYSCONFIG3_SMUTEA_10DB (0x3 << 12)
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#define SYSCONFIG3_VOLEXT (0x1 << 8) /* x */
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#define SYSCONFIG3_SKSNR (0xf << 4)
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#define SYSCONFIG3_SKSNRw(x) (((x) << 4) & SYSCONFIG3_SKSNR)
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#define SYSCONFIG3_SKCNT (0xf << 0)
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#define SYSCONFIG3_SKCNTw(x) (((x) << 0) & SYSCONFIG3_SKCNT)
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/* TEST1 (0x7) */
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/* 4700/01: 15=always 0, 13:0 = write with preexisting values! */
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/* 4702/03: 13:0 = write with preexisting values! */
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#define TEST1_XOSCEN (0x1 << 15) /* x */
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#define TEST1_AHIZEN (0x1 << 14)
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/* TEST2 (0x8) */
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/* 15:0 = write with preexisting values! */
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/* BOOTCONFIG (0x9) */
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/* 15:0 = write with preexisting values! */
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/* STATUSRSSI (0xA) */
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#define STATUSRSSI_RDSR (0x1 << 15) /* x */
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#define STATUSRSSI_STC (0x1 << 14)
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#define STATUSRSSI_SFBL (0x1 << 13)
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#define STATUSRSSI_AFCRL (0x1 << 12)
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#define STATUSRSSI_RDSS (0x1 << 11) /* x */
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#define STATUSRSSI_BLERA (0x3 << 9) /* x */
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#define STATUSRSSI_ST (0x1 << 8)
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#define STATUSRSSI_RSSI (0xff << 0)
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#define STATUSRSSI_RSSIr(x) ((x) & 0xff)
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/* READCHAN (0xB) */
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#define READCHAN_BLERB (0x3 << 14) /* x */
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#define READCHAN_BLERC (0x3 << 12) /* x */
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#define READCHAN_BLERD (0x3 << 10) /* x */
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#define READCHAN_READCHAN (0x3ff << 0)
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/* RDSA-D (0xC-0xF) */
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/* 4702/03: RDS Block A-D data */
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static bool tuner_present = false;
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static uint16_t cache[16];
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static struct mutex fmr_mutex SHAREDBSS_ATTR;
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/* reads <len> registers from radio at offset 0x0A into cache */
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static void si4700_read(int len)
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{
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int i;
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unsigned char buf[32];
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unsigned char *ptr = buf;
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uint16_t data;
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fmradio_i2c_read(I2C_ADR, buf, len * 2);
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for (i = 0; i < len; i++) {
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data = ptr[0] << 8 | ptr[1];
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cache[(i + STATUSRSSI) & 0xF] = data;
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ptr += 2;
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}
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}
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/* writes <len> registers from cache to radio at offset 0x02 */
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static void si4700_write(int len)
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{
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int i;
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unsigned char buf[32];
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unsigned char *ptr = buf;
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uint16_t data;
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for (i = 0; i < len; i++) {
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data = cache[(i + POWERCFG) & 0xF];
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*ptr++ = (data >> 8) & 0xFF;
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*ptr++ = data & 0xFF;
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}
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fmradio_i2c_write(I2C_ADR, buf, len * 2);
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}
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/* Hide silly, wrapped and continuous register reading and make interface
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* appear sane and normal. This also makes the driver compatible with
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* using the 3-wire interface. */
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static uint16_t si4700_read_reg(int reg)
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{
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si4700_read(((reg - STATUSRSSI) & 0xF) + 1);
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return cache[reg];
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}
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static void si4700_write_reg(int reg, uint16_t value)
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{
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cache[reg] = value;
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si4700_write(((reg - POWERCFG) & 0xF) + 1);
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}
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static void si4700_write_masked(int reg, uint16_t bits, uint16_t mask)
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{
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si4700_write_reg(reg, (cache[reg] & ~mask) | (bits & mask));
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}
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static void si4700_write_set(int reg, uint16_t mask)
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{
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si4700_write_reg(reg, cache[reg] | mask);
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}
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static void si4700_write_clear(int reg, uint16_t mask)
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{
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si4700_write_reg(reg, cache[reg] & ~mask);
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}
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#ifndef SI4700_USE_MO_ST_I
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/* Poll i2c for the stereo status */
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bool si4700_st(void)
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{
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return (si4700_read_reg(STATUSRSSI) & STATUSRSSI_ST) >> 8;
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}
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#endif /* ndef SI4700_USE_MO_ST_I */
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static void si4700_sleep(int snooze)
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{
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if (snooze)
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{
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/** power down **/
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#ifdef HAVE_RDS_CAP
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if (cache[CHIPID] & CHIPID_DEV_0) {
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si4700_rds_powerup(false);
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si4700_write_clear(SYSCONFIG1, SYSCONFIG1_RDS | SYSCONFIG1_RDSIEN);
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}
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#endif
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/* ENABLE high, DISABLE high */
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si4700_write_set(POWERCFG,
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POWERCFG_DISABLE | POWERCFG_ENABLE);
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/* Bits self-clear once placed in powerdown. */
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cache[POWERCFG] &= ~(POWERCFG_DISABLE | POWERCFG_ENABLE);
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tuner_power(false);
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}
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else
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{
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tuner_power(true);
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/* read all registers */
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si4700_read(16);
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#ifdef SI4700_USE_INTERNAL_OSCILLATOR
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/* Enable the internal oscillator
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(Si4702-16 needs this register to be initialised to 0x100) */
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si4700_write_set(TEST1, TEST1_XOSCEN | 0x100);
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sleep(HZ/2);
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#endif
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/** power up **/
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/* ENABLE high, DISABLE low */
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si4700_write_masked(POWERCFG, POWERCFG_ENABLE,
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POWERCFG_DISABLE | POWERCFG_ENABLE);
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sleep(110 * HZ / 1000);
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/* init register cache */
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si4700_read(16);
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#ifdef SI4700_USE_MO_ST_I
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si4700_write_masked(SYSCONFIG1, SYSCONFIG1_GPIO3_MO_ST_I,
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SYSCONFIG1_GPIO3);
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#endif
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/* set mono->stereo switching RSSI range to lowest setting */
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si4700_write_masked(SYSCONFIG1, SYSCONFIG1_BLNDADJ_19_37_RSSI,
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SYSCONFIG1_BLNDADJ);
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si4700_write_masked(SYSCONFIG2,
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SYSCONFIG2_SEEKTHw(SEEK_THRESHOLD) |
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SYSCONFIG2_VOLUMEw(0xF),
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SYSCONFIG2_VOLUME | SYSCONFIG2_SEEKTH);
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#ifdef HAVE_RDS_CAP
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/* enable RDS and RDS interrupt if supported (bit 9 of CHIPID) */
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if (cache[CHIPID] & CHIPID_DEV_0) {
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/* Is Si4701/2/3 - Enable RDS and interrupt */
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si4700_write_set(SYSCONFIG1, SYSCONFIG1_RDS | SYSCONFIG1_RDSIEN);
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si4700_write_masked(SYSCONFIG1, SYSCONFIG1_GPIO2_STC_RDS_I,
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SYSCONFIG1_GPIO2);
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si4700_rds_powerup(true);
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}
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#endif
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}
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}
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bool si4700_detect(void)
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{
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if (!tuner_present) {
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tuner_power(true);
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tuner_present = (si4700_read_reg(DEVICEID) == 0x1242);
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tuner_power(false);
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}
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return tuner_present;
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}
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void si4700_init(void)
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{
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mutex_init(&fmr_mutex);
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/* check device id */
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if (si4700_detect()) {
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/* make sure the tuner goes into a well-defined powered-off state */
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si4700_sleep(0);
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si4700_sleep(1);
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#ifdef HAVE_RDS_CAP
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rds_init();
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si4700_rds_init();
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#endif
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}
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}
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static void si4700_set_frequency(int freq)
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{
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static const unsigned int spacings[3] =
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{
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200000, /* SYSCONFIG2_SPACE_200KHZ */
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100000, /* SYSCONFIG2_SPACE_100KHZ */
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50000, /* SYSCONFIG2_SPACE_50KHZ */
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};
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static const unsigned int bands[3] =
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{
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87500000, /* SYSCONFIG2_BAND_875_1080 */
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76000000, /* SYSCONFIG2_BAND_760_1080 */
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76000000, /* SYSCONFIG2_BAND_760_900 */
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};
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/* check BAND and spacings */
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int space = SYSCONFIG2_SPACEr(cache[SYSCONFIG2]);
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int band = SYSCONFIG2_BANDr(cache[SYSCONFIG2]);
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int chan = (freq - bands[band]) / spacings[space];
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int readchan;
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do
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{
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/* tuning should be done within 60 ms according to the datasheet */
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si4700_write_reg(CHANNEL, CHANNEL_CHANw(chan) | CHANNEL_TUNE);
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sleep(HZ * 60 / 1000);
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/* get tune result */
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readchan = si4700_read_reg(READCHAN) & READCHAN_READCHAN;
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si4700_write_clear(CHANNEL, CHANNEL_TUNE);
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} while (!((cache[STATUSRSSI] & STATUSRSSI_STC) && (readchan == chan)));
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}
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static int si4700_tuned(void)
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{
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/* Primitive tuning check: sufficient level and AFC not railed */
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uint16_t status = si4700_read_reg(STATUSRSSI);
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if (STATUSRSSI_RSSIr(status) >= SEEK_THRESHOLD &&
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(status & STATUSRSSI_AFCRL) == 0)
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return 1;
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return 0;
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}
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static void si4700_set_region(int region)
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{
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const struct fm_region_data *rd = &fm_region_data[region];
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int band = (rd->freq_min == 76000000) ? 2 : 0;
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int spacing = (100000 / rd->freq_step);
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int deemphasis = (rd->deemphasis == 50) ? SYSCONFIG1_DE : 0;
|
|
|
|
uint16_t bandspacing = SYSCONFIG2_BANDw(band) |
|
|
SYSCONFIG2_SPACEw(spacing);
|
|
si4700_write_masked(SYSCONFIG1, deemphasis, SYSCONFIG1_DE);
|
|
si4700_write_masked(SYSCONFIG2, bandspacing,
|
|
SYSCONFIG2_BAND | SYSCONFIG2_SPACE);
|
|
}
|
|
|
|
/* tuner abstraction layer: set something to the tuner */
|
|
int si4700_set(int setting, int value)
|
|
{
|
|
int val = 1;
|
|
|
|
if(!tuner_powered() && setting != RADIO_SLEEP)
|
|
return -1;
|
|
|
|
mutex_lock(&fmr_mutex);
|
|
|
|
switch(setting)
|
|
{
|
|
case RADIO_SLEEP:
|
|
si4700_sleep(value);
|
|
break;
|
|
|
|
case RADIO_FREQUENCY:
|
|
#ifdef HAVE_RDS_CAP
|
|
rds_reset();
|
|
#endif
|
|
si4700_set_frequency(value);
|
|
break;
|
|
|
|
case RADIO_SCAN_FREQUENCY:
|
|
#ifdef HAVE_RDS_CAP
|
|
rds_reset();
|
|
#endif
|
|
si4700_set_frequency(value);
|
|
val = si4700_tuned();
|
|
break;
|
|
|
|
case RADIO_MUTE:
|
|
si4700_write_masked(POWERCFG, value ? 0 : POWERCFG_DMUTE,
|
|
POWERCFG_DMUTE);
|
|
break;
|
|
|
|
case RADIO_REGION:
|
|
si4700_set_region(value);
|
|
break;
|
|
|
|
case RADIO_FORCE_MONO:
|
|
si4700_write_masked(POWERCFG, value ? POWERCFG_MONO : 0,
|
|
POWERCFG_MONO);
|
|
break;
|
|
|
|
default:
|
|
val = -1;
|
|
break;
|
|
}
|
|
|
|
mutex_unlock(&fmr_mutex);
|
|
|
|
return val;
|
|
}
|
|
|
|
/* tuner abstraction layer: read something from the tuner */
|
|
int si4700_get(int setting)
|
|
{
|
|
int val = -1; /* default for unsupported query */
|
|
|
|
if(!tuner_powered() && setting != RADIO_PRESENT)
|
|
return -1;
|
|
|
|
mutex_lock(&fmr_mutex);
|
|
|
|
switch(setting)
|
|
{
|
|
case RADIO_PRESENT:
|
|
val = tuner_present;
|
|
break;
|
|
|
|
case RADIO_TUNED:
|
|
val = si4700_tuned();
|
|
break;
|
|
|
|
case RADIO_STEREO:
|
|
val = si4700_st();
|
|
break;
|
|
|
|
case RADIO_RSSI:
|
|
val = STATUSRSSI_RSSIr(si4700_read_reg(STATUSRSSI));
|
|
break;
|
|
|
|
case RADIO_RSSI_MIN:
|
|
val = RSSI_MIN;
|
|
break;
|
|
|
|
case RADIO_RSSI_MAX:
|
|
val = RSSI_MAX;
|
|
break;
|
|
}
|
|
|
|
mutex_unlock(&fmr_mutex);
|
|
|
|
return val;
|
|
}
|
|
|
|
void si4700_dbg_info(struct si4700_dbg_info *nfo)
|
|
{
|
|
memset(nfo->regs, 0, sizeof (nfo->regs));
|
|
|
|
mutex_lock(&fmr_mutex);
|
|
|
|
if (tuner_powered())
|
|
{
|
|
si4700_read(16);
|
|
memcpy(nfo->regs, cache, sizeof (nfo->regs));
|
|
}
|
|
|
|
mutex_unlock(&fmr_mutex);
|
|
}
|
|
|
|
#ifdef HAVE_RDS_CAP
|
|
|
|
#if (CONFIG_RDS & RDS_CFG_ISR)
|
|
static unsigned char isr_regbuf[(RDSD - STATUSRSSI + 1) * 2];
|
|
|
|
/* Called by RDS interrupt on target */
|
|
void si4700_rds_interrupt(void)
|
|
{
|
|
si4700_rds_read_raw_async(isr_regbuf, sizeof (isr_regbuf));
|
|
}
|
|
|
|
/* Handle RDS event from ISR */
|
|
void si4700_rds_process(void)
|
|
{
|
|
uint16_t rds_data[4];
|
|
int index = (RDSA - STATUSRSSI) * 2;
|
|
|
|
for (int i = 0; i < 4; i++) {
|
|
rds_data[i] = isr_regbuf[index] << 8 | isr_regbuf[index + 1];
|
|
index += 2;
|
|
}
|
|
|
|
rds_process(rds_data);
|
|
}
|
|
|
|
#else /* !(CONFIG_RDS & RDS_CFG_ISR) */
|
|
|
|
/* Handle RDS event from thread */
|
|
void si4700_rds_process(void)
|
|
{
|
|
mutex_lock(&fmr_mutex);
|
|
|
|
if (tuner_powered())
|
|
{
|
|
si4700_read_reg(RDSD);
|
|
rds_process(&cache[RDSA]);
|
|
}
|
|
|
|
mutex_unlock(&fmr_mutex);
|
|
}
|
|
#endif /* (CONFIG_RDS & RDS_CFG_ISR) */
|
|
|
|
#endif /* HAVE_RDS_CAP */
|
|
|