253 lines
7.7 KiB
C
253 lines
7.7 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2021 Aidan MacDonald
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include "audiohw.h"
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#include "sound.h"
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#include "panic.h"
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#include "pcm_sampr.h"
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#include "pcm_sw_volume.h"
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#include "system.h"
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#include "i2c-async.h"
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/* sample rates supported by the hardware */
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#define CAPS (SAMPR_CAP_192 | SAMPR_CAP_176 | \
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SAMPR_CAP_96 | SAMPR_CAP_88 | SAMPR_CAP_64 | \
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SAMPR_CAP_48 | SAMPR_CAP_44 | SAMPR_CAP_32 | \
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SAMPR_CAP_24 | SAMPR_CAP_22 | SAMPR_CAP_16 | \
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SAMPR_CAP_12 | SAMPR_CAP_11 | SAMPR_CAP_8)
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/* future proofing */
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#if (HW_SAMPR_CAPS & ~CAPS) != 0
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# error "incorrect HW_SAMPR_CAPS"
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#endif
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#ifndef HAVE_SW_VOLUME_CONTROL
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# error "AK4376 requires HAVE_SW_VOLUME_CONTROL!"
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#endif
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/* NOTE: At present, only the FiiO M3K uses this driver so the handling of
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* the clock / audio interface is limited to I2S slave, 16-bit samples, with
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* DAC master clock provided directly on the MCLK input pin, fitting the
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* clock setup of the M3K.
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*
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* Feel free to expand upon this if another target ever needs this driver.
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*/
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/* Converts HW_FREQ_XX constants to register values */
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static const uint8_t ak4376_fsel_to_hw[] = {
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HW_HAVE_192_(AK4376_FS_192,)
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HW_HAVE_176_(AK4376_FS_176,)
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HW_HAVE_96_(AK4376_FS_96,)
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HW_HAVE_88_(AK4376_FS_88,)
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HW_HAVE_64_(AK4376_FS_64,)
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HW_HAVE_48_(AK4376_FS_48,)
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HW_HAVE_44_(AK4376_FS_44,)
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HW_HAVE_32_(AK4376_FS_32,)
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HW_HAVE_24_(AK4376_FS_24,)
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HW_HAVE_22_(AK4376_FS_22,)
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HW_HAVE_16_(AK4376_FS_16,)
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HW_HAVE_12_(AK4376_FS_12,)
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HW_HAVE_11_(AK4376_FS_11,)
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HW_HAVE_8_(AK4376_FS_8,)
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};
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static int ak4376_regs[AK4376_NUM_REGS];
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void ak4376_open(void)
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{
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/* Initialize DAC state */
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for(int i = 0; i < AK4376_NUM_REGS; ++i)
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ak4376_regs[i] = -1;
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/* Initial reset after power-on */
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ak4376_set_pdn_pin(0);
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mdelay(1);
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ak4376_set_pdn_pin(1);
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mdelay(1);
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static const uint8_t init_config[] = {
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/* Ensure HPRHZ, HPLHZ are 0 */
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AK4376_REG_OUTPUT_MODE, 0x00,
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/* Mute all volume controls */
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AK4376_REG_MIXER, AK4376_MIX_LCH | (AK4376_MIX_RCH << 4),
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AK4376_REG_LCH_VOLUME, 0x80,
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AK4376_REG_RCH_VOLUME, 0x00,
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AK4376_REG_AMP_VOLUME, 0x00,
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/* Clock source = MCLK, divider = 1 */
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AK4376_REG_DAC_CLK_SRC, 0x00,
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AK4376_REG_DAC_CLK_DIV, 0x00,
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/* I2S slave mode, 16-bit samples */
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AK4376_REG_AUDIO_IF_FMT, 0x03,
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/* Recommended by datasheet */
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AK4376_REG_ADJUST1, 0x20,
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AK4376_REG_ADJUST2, 0x05,
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/* Power controls */
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AK4376_REG_PWR2, 0x33,
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AK4376_REG_PWR3, 0x01,
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AK4376_REG_PWR4, 0x03,
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};
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/* Write initial configuration prior to power-up */
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for(size_t i = 0; i < ARRAYLEN(init_config); i += 2)
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ak4376_write(init_config[i], init_config[i+1]);
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}
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void ak4376_close(void)
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{
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/* Shut off power */
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ak4376_write(AK4376_REG_PWR3, 0x00);
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ak4376_write(AK4376_REG_PWR4, 0x00);
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ak4376_write(AK4376_REG_PWR2, 0x00);
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/* PDN pin low */
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ak4376_set_pdn_pin(0);
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}
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void ak4376_write(int reg, int value)
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{
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/* Ensure value is sensible and differs from the last set value */
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if((value & 0xff) == value && ak4376_regs[reg] != value) {
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int r = i2c_reg_write1(AK4376_BUS, AK4376_ADDR, reg, value);
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if(r == I2C_STATUS_OK)
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ak4376_regs[reg] = value;
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else
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ak4376_regs[reg] = -1;
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}
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}
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int ak4376_read(int reg)
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{
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/* Only read from I2C if we don't already know the value */
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if(ak4376_regs[reg] < 0)
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ak4376_regs[reg] = i2c_reg_read1(AK4376_BUS, AK4376_ADDR, reg);
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return ak4376_regs[reg];
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}
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static int round_step_up(int x, int step)
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{
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int rem = x % step;
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if(rem > 0)
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rem -= step;
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return x - rem;
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}
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static void calc_volumes(int vol, int* dig, int* sw)
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{
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/* Apply digital volume */
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*dig = round_step_up(vol, AK4376_DIG_VOLUME_STEP);
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*dig = MIN(*dig, AK4376_DIG_VOLUME_MAX);
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*dig = MAX(*dig, AK4376_DIG_VOLUME_MIN);
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vol -= *dig;
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/* Seems that this is the allowable range for software volume */
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*sw = MIN(vol, 60);
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*sw = MAX(*sw, -730);
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vol -= *sw;
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}
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static int dig_vol_to_hw(int vol)
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{
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if(vol < AK4376_DIG_VOLUME_MIN) return 0;
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if(vol > AK4376_DIG_VOLUME_MAX) return 31;
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return (vol - AK4376_DIG_VOLUME_MIN) / AK4376_DIG_VOLUME_STEP + 1;
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}
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static int amp_vol_to_hw(int vol)
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{
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if(vol < AK4376_AMP_VOLUME_MIN) return 0;
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if(vol > AK4376_AMP_VOLUME_MAX) return 14;
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return (vol - AK4376_AMP_VOLUME_MIN) / AK4376_AMP_VOLUME_STEP + 1;
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}
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void ak4376_set_volume(int vol_l, int vol_r)
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{
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int amp;
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int dig_l, sw_l;
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int dig_r, sw_r;
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if(vol_l <= AK4376_MIN_VOLUME && vol_r <= AK4376_MIN_VOLUME) {
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/* Special case for full mute */
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amp = AK4376_AMP_VOLUME_MUTE;
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dig_l = dig_r = AK4376_DIG_VOLUME_MUTE;
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sw_l = sw_r = PCM_MUTE_LEVEL;
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} else {
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/* Amp is a mono control -- calculate based on the loudest channel.
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* The quieter channel then gets reduced more by digital controls. */
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amp = round_step_up(MAX(vol_l, vol_r), AK4376_AMP_VOLUME_STEP);
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amp = MIN(amp, AK4376_AMP_VOLUME_MAX);
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amp = MAX(amp, AK4376_AMP_VOLUME_MIN);
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/* Other controls are stereo */
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calc_volumes(vol_l - amp, &dig_l, &sw_l);
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calc_volumes(vol_r - amp, &dig_r, &sw_r);
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}
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ak4376_write(AK4376_REG_LCH_VOLUME, dig_vol_to_hw(dig_l) | (1 << 7));
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ak4376_write(AK4376_REG_RCH_VOLUME, dig_vol_to_hw(dig_r));
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ak4376_write(AK4376_REG_AMP_VOLUME, amp_vol_to_hw(amp));
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pcm_set_master_volume(sw_l, sw_r);
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}
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void ak4376_set_filter_roll_off(int val)
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{
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int reg = ak4376_read(AK4376_REG_FILTER);
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reg &= ~0xc0;
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reg |= (val & 3) << 6;
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ak4376_write(AK4376_REG_FILTER, reg);
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}
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void ak4376_set_freqmode(int fsel, int mult, int power_mode)
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{
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/* Calculate clock mode for frequency. Multipliers of 32/64 are only
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* for rates >= 256 KHz which are not supported by Rockbox, so they
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* are commented out -- but they're in the correct place. */
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int clock_mode = ak4376_fsel_to_hw[fsel];
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switch(mult) {
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/* case 32: */
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case 256:
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break;
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/* case 64: */
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case 512:
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clock_mode |= 0x20;
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break;
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case 1024:
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clock_mode |= 0x40;
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break;
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case 128:
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clock_mode |= 0x60;
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break;
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default:
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panicf("ak4376: bad master clock multiple %d", mult);
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return;
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}
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/* Handle the DSMLP bit in the MODE_CTRL register */
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int mode_ctrl = 0x00;
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if(power_mode || hw_freq_sampr[fsel] <= SAMPR_12)
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mode_ctrl |= 0x40;
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/* Program the new settings */
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ak4376_write(AK4376_REG_CLOCK_MODE, clock_mode);
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ak4376_write(AK4376_REG_MODE_CTRL, mode_ctrl);
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ak4376_write(AK4376_REG_PWR3, power_mode ? 0x11 : 0x01);
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}
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