ompayne
/
sicp
1
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

Update for exercise 3.32

This commit is contained in:
Oliver Payne 2022-09-28 22:37:25 +01:00
parent e506508c07
commit 44f4d79086
1 changed files with 9 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
circuit-simulator.rkt
View File

@ -439,3 +439,12 @@
;; In particular, for the half adder, the wire after the inverter remains at
;; 0 despite its input being 0. As a result, the sum is not set correctly.
;; Exercise 3.32
;; If we use a stack instead of a queue for the agenda segments, then for each segment
;; the tasks will be removed in the reverse order to that which they were added. In
;; the case of the and gate, the output value is calculated at the time of the signal change
;; (i.e. before the delay) and held in the closure. While the values of the input signals
;; will be played back in the correct order, the value of the output will be played back
;; in reverse. If the order of the inputs is: (0,0), (1,0), (1,1), (0,1), then the output
;; will be set to 0 by the last change and then 1 by the penultimate change, which is not
;; the correct answer.