los circuitos lógicos en este compendio están descritos en {verilog}, un lenguaje descriptor de hardware. esto con la idea de estandarizarlos, de facilitar simularlos e implementarlos en otros materiales, y de indicar su cualidad de red abstracta.
cada circuito indica un número de participantes que varía entre dos opciones. el número menor está calculado como el número de entradas más el número de compuertas. el otro número suma también el número de salidas del circuito completo, que de otra forma serían realizadas por alguna(s) de las compuertas.
utilizamos el lenguaje a nivel de {compuertas} lógicas solamente: cada compuerta se expresa como una función (and(), not(), or(), nor(), nand(), etc) donde el primer argumento es el nombre de la salida de la compuerta, y el o los otros argumentos son los nombres de las entradas.
específicamente, los circuitos están clasificados como los que usan compuertas habituales, o los que están construidos utilizando únicamente compuertas {nor}.
may this serve as a reference for non-electronic, human-scale, very-slow implementations of digital circuits that use a 7-segment display as an output.
=> ./img/diagram_7segmentdisplay.png 7 segment display with labels, from wikimedia commons (image)
hex-digit to seven-segment table:
```
a b c d e f g
0 1 1 1 1 1 1 0
1 0 1 1 0 0 0 0
2 1 1 0 1 1 0 1
3 1 1 1 1 0 0 1
4 0 1 1 0 0 1 1
5 1 0 1 1 0 1 1
6 1 0 1 1 1 1 1
7 1 1 1 0 0 0 0
8 1 1 1 1 1 1 1
9 1 1 1 1 0 1 1
A 1 1 1 0 1 1 1
b 0 0 1 1 1 1 1
C 1 0 0 1 1 1 0
d 0 1 1 1 1 0 1
E 1 0 0 1 1 1 1
F 1 0 0 0 1 1 1
```
## hexadecimal decoder
different gate-level implementations of a 4-bit to 7-segment display hexadecimal decoder: the input is a 4-bit binary number, and the output is the display showing the corresponding hexadecimal digit.
* straightforward version (S)
* simplified version (K)
* simplified version in NOR
* simple-simplified version (Z)
comparison of number of gates:
```
S K Z
NOT 4 4 4
2-input OR 0 1 29
3-input OR 0 10 0
4-input OR 15 10 0
2-input AND 0 0 3
3-input AND 0 3 4
4-input AND 3 3 2
5-input AND 2 1 0
6-input AND 2 0 0
total 26 32 42
```
in cases S and K, the gates AND,OR can be replaced with NOR.
### straightforward version
this circuit uses a complete "product of maxterms" for each of the segments.
the maxterms correspond to the numbers that turn off that specific segment.
``` verilog
// 4-bit hexadecimal to 7-segment decoder with traditional gates
module hex_to_7seg( b3, b2, b1, b0, a, b, c, d, e, f, g);
input wire b3, b2, b1, b0; // 4 bits as input
output wire a, b, c, d, e, f, g; // 7 segments as output
// we keep the maxterms: 1, 2, 4, 5, 7, 9, A, B, C, D
or G04( or1, b3, b2, b1, n0); // 0b0001, 1
or G05( or2, b3, b2, n1, b0); // 0b0010, 2
or G06( or4, b3, n2, b1, b0); // 0b0100, 4
or G07( or5, b3, n2, b1, n0); // 0b0101, 5
or G08( or7, b3, n2, n1, n0); // 0b0111, 7
or G09( or9, n3, b2, b1, n0); // 0b1001, 9
or G10( orA, n3, b2, n1, b0); // 0b1010, A
or G11( orB, n3, b2, n1, n0); // 0b1011, B
or G12( orC, n3, n2, b1, b0); // 0b1100, C
or G13( orD, n3, n2, b1, n0); // 0b1101, D
// 3-input ORs:
or G14(or111X, n3, n2, n1);
or G15(or11X0, n3, n2, b0);
or G16(or1X11, n3, n1, n0);
or G17(orX110, n2, n1, b0);
or G18(orX111, n2, n1, n0);
or G19(or010X, b3, n2, b1);
or G20(or00X1, b3, b2, n0);
or G21(or001X, b3, b2, n1);
or G22(or0X11, b3, n1, n0);
or G23(or000X, b3, b2, b1);
// 2-input OR:
or G24(or0XX1, b3, n0);
// each segment
and G25( a, or1, or4, orB, orD); // 4-inputs
and G26( b, or111X, or11X0, or1X11, orX110, or5); // 5-inputs
and G27( c, or111X, or11X0, or2); // 3-inputs
and G28( d, orX111, or1, or4, orA); // 4-inputs
and G29( e, or0XX1, or010X, or9); // 3-inputs
and G30( f, or00X1, or001X, or0X11, orD); // 4-inputs
and G31( g, or000X, or7, orC); // 3-inputs
endmodule
```
### simplified version, with NOR gates and cleaned up labels
this is the same circuit as above, but replacing the AND,OR gates with NOR gates (thanks to it being a "two-level product of maxterms" ciruit).
here the gates and their output wires are labelled GXX and gXX respectively, using octal numbering.
``` verilog
// 4-bit hexadecimal to 7-segment decoder with NOR gates
// "cleaned up" wire names
module hex_to_7seg( b3, b2, b1, b0, a, b, c, d, e, f, g);
input wire b3, b2, b1, b0; // 4 bits as input
output wire a, b, c, d, e, f, g; // 7 segments as output
wire g00, g01, g02, g03, g04, g05, g06, g07;
wire g10, g11, g12, g13, g14, g15, g16, g17;
wire g20, g21, g22, g23, g24, g25, g26, g27;
wire g30, g31, g32, g33, g34, g35, g36, g37;
// inversions:
not G00( g00, b0);
not G01( g01, b1);
not G02( g02, b2);
not G03( g03, b3);
// maxterms:
// we keep the maxterms: 1, 2, 4, 5, 7, 9, A, B, C, D
nor G04( g04, b3, b2, b1, g00); // 0b0001, 1
nor G05( g05, b3, b2, g01, b0); // 0b0010, 2
nor G06( g06, b3, g02, b1, b0); // 0b0100, 4
nor G07( g07, b3, g02, b1, g00); // 0b0101, 5
nor G10( g10, b3, g02, g01, g00); // 0b0111, 7
nor G11( g11, g03, b2, b1, g00); // 0b1001, 9
nor G12( g12, g03, b2, g01, b0); // 0b1010, A
nor G13( g13, g03, b2, g01, g00); // 0b1011, B
nor G14( g14, g03, g02, b1, b0); // 0b1100, C
nor G15( g15, g03, g02, b1, g00); // 0b1101, D
// 3-input:
nor G16(g16, g03, g02, g01);
nor G17(g17, g03, g02, b0);
nor G20(g20, g03, g01, g00);
nor G21(g21, g02, g01, b0);
nor G22(g22, g02, g01, g00);
nor G23(g23, b3, g02, b1);
nor G24(g24, b3, b2, g00);
nor G25(g25, b3, b2, g01);
nor G26(g26, b3, g01, g00);
nor G27(g27, b3, b2, b1);
// 2-input:
nor G30(g30, b3, g00);
// each segment
nor G31( g31, g04, g06, g13, g15); // 4-inputs
nor G32( g32, g16, g17, g20, g21, g07); // 5-inputs
nor G33( g33, g16, g17, g05); // 3-inputs
nor G34( g34, g22, g04, g06, g12); // 4-inputs
nor G35( g35, g30, g23, g11); // 3-inputs
nor G36( g36, g24, g25, g26, g15); // 4-inputs
nor G37( g37, g27, g10, g14); // 3-inputs
assign a = g31;
assign b = g32;
assign c = g33;
assign d = g34;
assign e = g35;
assign f = g36;
assign g = g37;
```
### simple-simplified version, with "normal" gates
in this circuit, repeated OR operations were "abbreviated": 4-input OR gates were replaced by 3 2-input OR gates, taking advantage of the fact that many of those 2-input ORs are common and can be reused.
here the transformation to NOR gates is not as straightforward: each OR that is an input for another OR, has to be inverted (adding a NOT) before being able to convert OR, AND to NORs.