notas sobre {poñg}, {bouncer-2d prototype} y ramificaciones
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@ -14,7 +14,7 @@ nos identificamos con las ideas del {permacomputing}.
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# investigación
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nuestra principal línea de exploración son {las danzas}, pero también diseñamos y desarrollamos {coloring computers}, y exploramos {beans computing}.
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nuestra principal línea de exploración son {las danzas}, pero también diseñamos y desarrollamos {coloring computers}, y exploramos {cómputo frijol}.
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¡nos encanta compartir! ya sea en tutoriales o pláticas y talleres.
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@ -1,14 +1,20 @@
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# beans computing
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lang=en es->{cómputo frijol}
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non-electronic {digital systems} based on manipulating beans according to simple logical rules.
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inspired by {the beans computer}, but going at a lower level. most of the times this is related to {paper computing}.
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the {computadora de papel} is also related as a beans-based, "higher level" computer.
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# projects and prototypes
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# projects
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{norpet} is a proof-of-concept for ideas we have about beans computing in an 8x8 grid or board.
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=> ./img/foto_norpet_02.png closeup photo of the norpet board completely solved in one of its states: the grid is full of either soy or black beans.
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# prototypes
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{bouncing ball logic} and {bouncer-2d prototype} provide some notes from the initial development of {poñg} around 12020.
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=> ./img/secuencia_bounce2d-8x6-0a3.gif a sequence of four frames showing two paper boards with black and soy beans in them: the one in the left contains the processing cells, and the one in the right looks like a screen composed of soy beans except for one, which seems to be moving from the top left corner to the bottom and right.
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# truth tables
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@ -0,0 +1,44 @@
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# bouncer2d-8x6 computadora de mesa (prototipo)
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lang=es en->{bouncer-2d prototype}
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computadora de mesa con pantalla monocromática de 8x6: no electrónica, a escala humana, y muy lenta. un experimento de {cómputo frijol}.
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siguiendo unas reglas simples, puedes colaborar con ella para computar y mostrar la animación de una pelota rebotando en las paredes de la pantalla, un cuado a la vez.
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=> ./img/secuencia_bounce2d-8x6-0a3.gif a sequence of four frames showing two paper boards with black and soy beans in them: the one in the left contains the processing cells, and the one in the right looks like a screen composed of soy beans except for one, which seems to be moving from the top left corner to the bottom and right.
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# descargas
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=> https://ipfs.io/ipfs/QmfQwdoc68dPXnGTspTiWu8xjpCLGUaH7YYFUmx84YUtwS/ bouncer2d-8x6 lista para ser impresa (pdf)
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# estructura
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como podrás ver, la computadora consiste en dos páginas, ambas con celdas impresas.
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podemos verla como dividida en cuatro secciones.
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primera página:
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* fila superior: estado actual de la máquina, codificado
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* bloque de enmedio: celdas de procesamiento
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* fila inferior: estado siguiente de la máquina, codificado
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segunda página:
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* pantalla monocromática de 8x6 pixeles/celdas
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# modo de uso:
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* antes que nada, elige dos clases de elementos múltiples que tengas, A y B (por ejemplo, A="frijoles" y B="garbanzos)
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* cada celda solo puede tener uno de esos elementos en un momento dado
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## para la fila superior (estado actual)
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* si esta es la primera iteración, coloca en esta fila una combinación arbitraria de elementos (por ejemplo, todas las celdas con garbanzos en ellas)
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* de no ser así, cuando termines una iteración y estés lista para empezar una nueva, transfiere los elementos de la fila inferior (estado siguiente) hacia la superior, manteniendo el mismo orden. así, el "estado siguiente" se convierte en el "estado actual"
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## para las demás celdas
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* observa las celdas de la computadora: cada una tiene su nombre hasta arriba, y una lista de 1 a 3 nombres que corresponden a sus "entradas".
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* en cada celda, acuérdate y aplica la regla: coloca un elemento de tipo A en su interior solamente cuando todas sus entradas son de tipo B. en cualquier otro caso, coloca un elemento de tipo B.
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* por ejemplo, regresando a los frijoles y garbanzos: "coloca un frijol en la celda cuando todas sus entradas tienen garbanzos. si no es así, coloca un garbanzo"
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* cuando termines de iterar en todas las celdas, habrás completado un cuadro de la animación. ¡captúralo de alguna manera para que lo compares con los que sigan!
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@ -0,0 +1,42 @@
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# bouncer2d-8x6 tabletop computer (prototype)
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lang=en es->{bouncer-2d prototipo}
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a tabletop non-electronic, human-scale, very-slow computer with an 8x6 monochromatic screen. a prototype of {beans computing}.
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following a simple set of rules, you can collaborate with it to compute and display an animation of a ball bouncing in the walls of the screen, one frame at a time.
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=> ./img/secuencia_bounce2d-8x6-0a3.gif a sequence of four frames showing two paper boards with black and soy beans in them: the one in the left contains the processing cells, and the one in the right looks like a screen composed of soy beans except for one, which seems to be moving from the top left corner to the bottom and right.
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# downloads
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=> => https://ipfs.io/ipfs/QmfQwdoc68dPXnGTspTiWu8xjpCLGUaH7YYFUmx84YUtwS/ bouncer2d-8x6 ready to be printed (pdf)
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# structure
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the computer has two pages, both of them with "cells". it has a total of four sections.
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first page:
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* top row: state of the machine (encoded)
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* middle block: process cells
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* bottom row: next state of the machine (encoded)
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second page:
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* 8x6 monochromatic screen
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# how to use:
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* first of all, choose two classes of elements, A and B (e.g. A="black beans" and B="chickpeas").
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* each cell can only have one of those elements at a given time.
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## for the top row
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* if this is the first iteration, fill it with an arbitrary combination of your elements (e.g. all the cells with a chickpea in each)
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* otherwise, when you finish an iteration and you are ready to start a new one, transfer the elements from the bottom row to the top row, keeping the same order.
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## for all the other cells
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* observe the cells in the computer: each one has a name at the top, and a list of 1 to 3 cell names that correspond to its inputs.
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* for each cell, remember and apply the rule: put an element of class A inside the cell only when all of its inputs are B. otherwise put inside an element of class B.
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* example rule: put a black bean inside the cell only when all of its inputs are chickpeas. otherwise, put a chickpea inside.
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* when you finish iterating through all the cells, you would have completed a frame of the animation in the screen. capture it somehow!
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@ -0,0 +1,209 @@
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# bouncing ball logic
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lang=en
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may this serve as a reference for non-electronic, human-scale, very-slow implementations of digital circuits that embody a virtual ball bouncing in a screen.
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these notes emerged from the work around {poñg}, "a human-scale digital videogame, with logic provided by people".
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# 1-dimension
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## 4-pixels wide screen
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the ball is a pixel that bounces back and forth.
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description of the logic in {verilog}:
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```
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// bouncing ball (pixel) in a 4-pixels screen
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// using NOR gates
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module onedimensional_bounce( E2, E1, E0, P3, P2, P1, P0, NE2, NE1, NE0 );
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input wire E2, E1, E0; // curent state
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output wire P3, P2, P1, P0; // pixels
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output wire NE2, NE1, NE0; // next state
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// inversions
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wire nE2, nE1, nE0;
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// ors
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wire NE0_1, NE0_2, NE1_2;
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// input inversions (3 gates)
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not g00( nE0, E0);
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not g01( nE1, E1);
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not g02( nE2, E2);
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// NE2
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assign NE2 = E1;
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// NE1
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nor g03( NE1_2, nE2, nE0);
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nor g04( NE1, P0, NE1_2);
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// NE0
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nor g05( NE0_1, nE2, E1, nE0);
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nor g06( NE0_2, E2, nE1, nE0);
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nor g07( NE0, NE0_1, NE0_2);
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// pixels
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nor g08( P3, nE1, E0);
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nor g09( P2, nE1, nE0);
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nor g10( P1, E1, nE0);
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nor g11( P0, E1, E0); // also "NE1_1"
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endmodule
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```
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### board and cards implementation
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compatible with {beans computing}: use two classes of beans to indicate a 1 or a 0.
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current state:
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```
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+----+----+----+
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| i2 | i1 | i0 |
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+----+----+----+
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```
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process helpers
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```
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+----+----+----+----+----+----+
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| p5 | p4 | p3 | p2 | p1 | p0 |
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+----+----+----+----+----+----+
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```
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next state and screen:
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```
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+----+----+----+ +----+----+----+----+
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| o6 | o5 | o4 | | o3 | o2 | o1 | o0 |
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+----+----+----+ +----+----+----+----+
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```
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the NOR-based cards for process and output cells:
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process helpers:
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```
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p0: i0
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p1: i1
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p2: i2
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p3: p2, p0
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p4: p2, i1, p0
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p5: i2, p1, p0
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```
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next state:
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```
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o6: p1
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o5: o0, p3
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o4: p4, p5
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```
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screen:
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```
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o3: p1, i0
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o2: p1, p0
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o1: i1, p0
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o0: i1, i0
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```
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(card p0 would be read: p0 is 1 when i0 is 0, and it's 0 otherwise; card p5 would be read: p5 is 1 when all i2, p1 and p0 are 0, and it's 0 otherwise)
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# 2-dimensions
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## 8x6 screen
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the following description, converted into a gate-level representation, results in the {bouncer-2d prototype}. the notes of how that process happened have to be recovered and documented here.
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### high-level verilog code
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```
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module bouncer2d
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#(
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parameter PIXELSW = 8,
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parameter PIXELSH = 6
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)
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(
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input [$clog2(PIXELSW)-1:0] posx,
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input [$clog2(PIXELSH)-1:0] posy,
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input dirx,
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input diry,
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output [$clog2(PIXELSW)-1:0] newposx,
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output [$clog2(PIXELSH)-1:0] newposy,
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output newdirx,
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output newdiry,
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output [(PIXELSW*PIXELSH)-1:0] screen
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);
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bouncer1d #( .NPIXELS( PIXELSW)) bouncex (
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.pos( posx ),
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.dir( dirx ),
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.newpos( newposx ),
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.newdir( newdirx )
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);
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bouncer1d #( .NPIXELS( PIXELSH)) bouncey (
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.pos( posy ),
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.dir( diry ),
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.newpos( newposy ),
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.newdir( newdiry )
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);
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screen_decoder #(.PIXELSW(PIXELSW), .PIXELSH( PIXELSH ))
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decoder (
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.posx( posx ),
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.posy( posy ),
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.screen( screen )
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);
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endmodule // bouncer2d
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module screen_decoder
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#(
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parameter PIXELSW = 8,
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parameter PIXELSH = 6
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)
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(
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input [$clog2(PIXELSW)-1:0] posx,
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input [$clog2(PIXELSH)-1:0] posy,
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output [(PIXELSW*PIXELSH)-1:0] screen
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);
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// decoder!
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genvar c, r;
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generate
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for(c=0; c<PIXELSW; c = c + 1) begin
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for(r=0; r<PIXELSH; r = r + 1) begin
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assign screen[c + r*PIXELSW] = (posx==c) && (posy==r);
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end
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end
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endgenerate
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// another possibility, less effective while synthesizing
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// assign screen = (1<<posx) << (posy*PIXELSW);
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endmodule // screen_decoder
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module bouncer1d
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#( parameter NPIXELS = 8)
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(
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input [$clog2(NPIXELS)-1:0] pos,
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input dir, // 1 inc, 0 dec
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output [$clog2(NPIXELS)-1:0] newpos,
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output newdir
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);
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/* //without edge-cases
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assign newdir = (dir==1 && pos==(NPIXELS-2)) ? 0 : (dir==0 && pos==1) ? 1 : dir;
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assign newpos = (dir==1) ? pos + 1 : pos - 1;
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*/
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// with edge cases (and less gates when synthesizing!)
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assign newdir = (pos==0) ? 1 : (pos>=NPIXELS-1) ? 0 : (dir==1 && pos==NPIXELS-2) || (dir==0 && pos==1) ? ~dir : dir;
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assign newpos = (pos==0) ? 1 : (pos>=NPIXELS-1) ? NPIXELS - 2 : (dir==1)? pos + 1 : pos -1;
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endmodule
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```
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@ -21,6 +21,26 @@ a coloring decoder built with NOT (triangle), AND (semicircle), and OR (the othe
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=> https://opguides.info/engineering/circuits/digitallogic/ colored and animated version by Vega
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=> https://ipfs.io/ipfs/QmZv53hr7QEzxrPaRNpiyU9VUNHw9UgyaTUqYD9x9iFpNA/dibujo_20201207_hex7segdecoder.png download the decoder in full size 1487x3057 (png, ~446KB)
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## instructions
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you use two colors to set the state of 4 "bits" at the top circles.
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one color stands for "1", the other for "0".
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what number, according to the conventions, would these 4 bits represent?
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and what hexadecimal digit would correspond to that number?
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you transmit those states/colors by coloring the wires.
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the wires lead to three possible types of gates, all of them with their input(s) above, and their output below:
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* NOT, a triangle: the output is the opposite color of the input
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* AND, a semicircle: the output is color "1" only when ALL inputs are also color "1"; otherwise the output is color "0"
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* OR, the other shape (?): the output is color "1" when ANY of the inputs are color "1"; otherwise the output is color "0".
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you finish coloring, and you see the digit in the display as a result!
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# computadora no(r)pal (12019)
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=> ./img/dibujo_20190715-norpalera-fulladder_blanco_small.png logic circuit in the shape of nopal
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@ -6,7 +6,7 @@ estos incluyen, claro está, a las:
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=> ./danzas_compuertas.gmi {danzas compuertas}
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=> ./coloring_computers.gmi {coloring computers}
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=> ./beans_computing.gmi {beans computing}
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=> ./cómputo_frijol.gmi {cómputo frijol}
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usamos la convención de utilizar dos valores posibles: 1 para denominar arriba, o verdadero, y 0 para denominar abajo, o falso.
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@ -0,0 +1,13 @@
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# cómputo frijol
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lang=es es->{beans computing}
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sistemas digitales no electrónicos basados en manipular frijoles de acuerdo a reglas lógicas simples.
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# proyectos
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{norpet mascota digital} fue una prueba de concepto de cómputo frijol en tableros de 8x8.
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=> ./img/foto_norpet_02.png foto del tablero de norpet completamente lleno en uno de sus estados: la cuadrícula está llena de frijoles negros y de soya, uno en cada casilla.
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# prototipos
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el {bouncer-2d prototipo} surge del desarrollo inicial de la {propuesta poñg}.
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=> ./img/secuencia_bounce2d-8x6-0a3.gif a sequence of four frames showing two paper boards with black and soy beans in them: the one in the left contains the processing cells, and the one in the right looks like a screen composed of soy beans except for one, which seems to be moving from the top left corner to the bottom and right.
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Binary file not shown.
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After Width: | Height: | Size: 8.7 KiB |
Binary file not shown.
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After Width: | Height: | Size: 515 KiB |
339
src/logiteca.gmo
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@ -318,3 +318,342 @@ nor C12(r, p7, p8, p9, p10);
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endmodule
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```
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# 7-segment display logic
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may this serve as a reference for non-electronic, human-scale, very-slow implementations of digital circuits that use a 7-segment display as an output.
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=> ./img/diagram_7segmentdisplay.png 7 segment display with labels, from wikimedia commons (image)
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hex-digit to seven-segment table:
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```
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a b c d e f g
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0 1 1 1 1 1 1 0
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1 0 1 1 0 0 0 0
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2 1 1 0 1 1 0 1
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3 1 1 1 1 0 0 1
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4 0 1 1 0 0 1 1
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5 1 0 1 1 0 1 1
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6 1 0 1 1 1 1 1
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7 1 1 1 0 0 0 0
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8 1 1 1 1 1 1 1
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9 1 1 1 1 0 1 1
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A 1 1 1 0 1 1 1
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b 0 0 1 1 1 1 1
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C 1 0 0 1 1 1 0
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d 0 1 1 1 1 0 1
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E 1 0 0 1 1 1 1
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F 1 0 0 0 1 1 1
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```
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## hexadecimal decoder
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|
||||
different gate-level implementations of a 4-bit to 7-segment display hexadecimal decoder: the input is a 4-bit binary number, and the output is the display showing the corresponding hexadecimal digit.
|
||||
|
||||
* straightforward version (S)
|
||||
* simplified version (K)
|
||||
* simplified version in NOR
|
||||
* simple-simplified version (Z)
|
||||
|
||||
comparison of number of gates:
|
||||
|
||||
```
|
||||
S K Z
|
||||
NOT 4 4 4
|
||||
2-input OR 0 1 29
|
||||
3-input OR 0 10 0
|
||||
4-input OR 15 10 0
|
||||
2-input AND 0 0 3
|
||||
3-input AND 0 3 4
|
||||
4-input AND 3 3 2
|
||||
5-input AND 2 1 0
|
||||
6-input AND 2 0 0
|
||||
|
||||
total 26 32 42
|
||||
```
|
||||
in cases S and K, the gates AND,OR can be replaced with NOR.
|
||||
|
||||
|
||||
### straightforward version
|
||||
|
||||
this circuit uses a complete "product of maxterms" for each of the segments.
|
||||
|
||||
the maxterms correspond to the numbers that turn off that specific segment.
|
||||
|
||||
``` verilog
|
||||
// 4-bit hexadecimal to 7-segment decoder with traditional gates
|
||||
module hex_to_7seg( b3, b2, b1, b0, a, b, c, d, e, f, g);
|
||||
|
||||
input wire b3, b2, b1, b0; // 4 bits as input
|
||||
output wire a, b, c, d, e, f, g; // 7 segments as output
|
||||
|
||||
// inversions:
|
||||
wire n3,n2,n1,n0;
|
||||
// maxterms:
|
||||
wire orF, orE, orD, orC, orB, orA, or9, or7, or6, or5, or4, or3, or2, or1, or0;
|
||||
|
||||
// inversions:
|
||||
not G00( n0, b0);
|
||||
not G01( n1, b1);
|
||||
not G02( n2, b2);
|
||||
not G03( n3, b3);
|
||||
|
||||
// maxterms:
|
||||
or G04( or0, b3, b2, b1, b0); // 0b0000, 0
|
||||
or G05( or1, b3, b2, b1, n0); // 0b0001, 1
|
||||
or G06( or2, b3, b2, n1, b0); // 0b0010, 2
|
||||
or G07( or3, b3, b2, n1, n0); // 0b0011, 3
|
||||
or G08( or4, b3, n2, b1, b0); // 0b0100, 4
|
||||
or G09( or5, b3, n2, b1, n0); // 0b0101, 5
|
||||
or G10( or6, b3, n2, n1, b0); // 0b0110, 6
|
||||
or G11( or7, b3, n2, n1, n0); // 0b0111, 7
|
||||
|
||||
or G12( or9, n3, b2, b1, n0); // 0b1001, 9
|
||||
or G13( orA, n3, b2, n1, b0); // 0b1010, A
|
||||
or G14( orB, n3, b2, n1, n0); // 0b1011, B
|
||||
or G15( orC, n3, n2, b1, b0); // 0b1100, C
|
||||
or G16( orD, n3, n2, b1, n0); // 0b1101, D
|
||||
or G17( orE, n3, n2, n1, b0); // 0b1110, E
|
||||
or G18( orF, n3, n2, n1, n0); // 0b1111, F
|
||||
|
||||
// each segment (see table above)
|
||||
and G19( a, or1, or4, orB, orD);
|
||||
and G20( b, or5, or6, orB, orC, orE, orF);
|
||||
and G21( c, or2, orC, orE, orF);
|
||||
and G22( d, or1, or4, or7, orA, orF);
|
||||
and G23( e, or1, or3, or4, or5, or7, or9);
|
||||
and G24( f, or1, or2, or3, or7, orD);
|
||||
and G25( g, or0, or1, or7, orC);
|
||||
|
||||
endmodule
|
||||
```
|
||||
|
||||
### simplified version
|
||||
|
||||
this first simplification consists in reducing the number of inputs in the maxterms.
|
||||
|
||||
the general architecture stays the same: one level of ORs, and one level of ANDs.
|
||||
|
||||
``` verilog
|
||||
// 4-bit hexadecimal to 7-segment decoder with traditional gates, "simplified"
|
||||
module hex_to_7seg( b3, b2, b1, b0, a, b, c, d, e, f, g);
|
||||
|
||||
input wire b3, b2, b1, b0; // 4 bits as input
|
||||
output wire a, b, c, d, e, f, g; // 7 segments as output
|
||||
|
||||
// inversions:
|
||||
wire n3,n2,n1,n0;
|
||||
// maxterms:
|
||||
wire orD, orC, orB, orA, or9, or7, or5, or4, or2, or1;
|
||||
|
||||
// others:
|
||||
wire or111X, or11X0, or1X11, orX110, orX111, or010X, or00X1, or001X, or0X11, or000X;
|
||||
wire or0XX1;
|
||||
|
||||
// inversions:
|
||||
not G00( n0, b0);
|
||||
not G01( n1, b1);
|
||||
not G02( n2, b2);
|
||||
not G03( n3, b3);
|
||||
|
||||
// maxterms:
|
||||
// we keep the maxterms: 1, 2, 4, 5, 7, 9, A, B, C, D
|
||||
or G04( or1, b3, b2, b1, n0); // 0b0001, 1
|
||||
or G05( or2, b3, b2, n1, b0); // 0b0010, 2
|
||||
or G06( or4, b3, n2, b1, b0); // 0b0100, 4
|
||||
or G07( or5, b3, n2, b1, n0); // 0b0101, 5
|
||||
or G08( or7, b3, n2, n1, n0); // 0b0111, 7
|
||||
or G09( or9, n3, b2, b1, n0); // 0b1001, 9
|
||||
or G10( orA, n3, b2, n1, b0); // 0b1010, A
|
||||
or G11( orB, n3, b2, n1, n0); // 0b1011, B
|
||||
or G12( orC, n3, n2, b1, b0); // 0b1100, C
|
||||
or G13( orD, n3, n2, b1, n0); // 0b1101, D
|
||||
|
||||
// 3-input ORs:
|
||||
or G14(or111X, n3, n2, n1);
|
||||
or G15(or11X0, n3, n2, b0);
|
||||
or G16(or1X11, n3, n1, n0);
|
||||
or G17(orX110, n2, n1, b0);
|
||||
or G18(orX111, n2, n1, n0);
|
||||
or G19(or010X, b3, n2, b1);
|
||||
or G20(or00X1, b3, b2, n0);
|
||||
or G21(or001X, b3, b2, n1);
|
||||
or G22(or0X11, b3, n1, n0);
|
||||
or G23(or000X, b3, b2, b1);
|
||||
|
||||
// 2-input OR:
|
||||
or G24(or0XX1, b3, n0);
|
||||
|
||||
// each segment
|
||||
and G25( a, or1, or4, orB, orD); // 4-inputs
|
||||
and G26( b, or111X, or11X0, or1X11, orX110, or5); // 5-inputs
|
||||
and G27( c, or111X, or11X0, or2); // 3-inputs
|
||||
and G28( d, orX111, or1, or4, orA); // 4-inputs
|
||||
and G29( e, or0XX1, or010X, or9); // 3-inputs
|
||||
and G30( f, or00X1, or001X, or0X11, orD); // 4-inputs
|
||||
and G31( g, or000X, or7, orC); // 3-inputs
|
||||
|
||||
endmodule
|
||||
```
|
||||
|
||||
### simplified version, with NOR gates and cleaned up labels
|
||||
|
||||
this is the same circuit as above, but replacing the AND,OR gates with NOR gates (thanks to it being a "two-level product of maxterms" ciruit).
|
||||
|
||||
here the gates and their output wires are labelled GXX and gXX respectively, using octal numbering.
|
||||
|
||||
``` verilog
|
||||
// 4-bit hexadecimal to 7-segment decoder with NOR gates
|
||||
// "cleaned up" wire names
|
||||
module hex_to_7seg( b3, b2, b1, b0, a, b, c, d, e, f, g);
|
||||
|
||||
input wire b3, b2, b1, b0; // 4 bits as input
|
||||
output wire a, b, c, d, e, f, g; // 7 segments as output
|
||||
|
||||
wire g00, g01, g02, g03, g04, g05, g06, g07;
|
||||
wire g10, g11, g12, g13, g14, g15, g16, g17;
|
||||
wire g20, g21, g22, g23, g24, g25, g26, g27;
|
||||
wire g30, g31, g32, g33, g34, g35, g36, g37;
|
||||
|
||||
// inversions:
|
||||
not G00( g00, b0);
|
||||
not G01( g01, b1);
|
||||
not G02( g02, b2);
|
||||
not G03( g03, b3);
|
||||
|
||||
// maxterms:
|
||||
// we keep the maxterms: 1, 2, 4, 5, 7, 9, A, B, C, D
|
||||
nor G04( g04, b3, b2, b1, g00); // 0b0001, 1
|
||||
nor G05( g05, b3, b2, g01, b0); // 0b0010, 2
|
||||
nor G06( g06, b3, g02, b1, b0); // 0b0100, 4
|
||||
nor G07( g07, b3, g02, b1, g00); // 0b0101, 5
|
||||
nor G10( g10, b3, g02, g01, g00); // 0b0111, 7
|
||||
nor G11( g11, g03, b2, b1, g00); // 0b1001, 9
|
||||
nor G12( g12, g03, b2, g01, b0); // 0b1010, A
|
||||
nor G13( g13, g03, b2, g01, g00); // 0b1011, B
|
||||
nor G14( g14, g03, g02, b1, b0); // 0b1100, C
|
||||
nor G15( g15, g03, g02, b1, g00); // 0b1101, D
|
||||
|
||||
// 3-input:
|
||||
nor G16(g16, g03, g02, g01);
|
||||
nor G17(g17, g03, g02, b0);
|
||||
nor G20(g20, g03, g01, g00);
|
||||
nor G21(g21, g02, g01, b0);
|
||||
nor G22(g22, g02, g01, g00);
|
||||
nor G23(g23, b3, g02, b1);
|
||||
nor G24(g24, b3, b2, g00);
|
||||
nor G25(g25, b3, b2, g01);
|
||||
nor G26(g26, b3, g01, g00);
|
||||
nor G27(g27, b3, b2, b1);
|
||||
|
||||
// 2-input:
|
||||
nor G30(g30, b3, g00);
|
||||
|
||||
// each segment
|
||||
nor G31( g31, g04, g06, g13, g15); // 4-inputs
|
||||
nor G32( g32, g16, g17, g20, g21, g07); // 5-inputs
|
||||
nor G33( g33, g16, g17, g05); // 3-inputs
|
||||
nor G34( g34, g22, g04, g06, g12); // 4-inputs
|
||||
nor G35( g35, g30, g23, g11); // 3-inputs
|
||||
nor G36( g36, g24, g25, g26, g15); // 4-inputs
|
||||
nor G37( g37, g27, g10, g14); // 3-inputs
|
||||
|
||||
assign a = g31;
|
||||
assign b = g32;
|
||||
assign c = g33;
|
||||
assign d = g34;
|
||||
assign e = g35;
|
||||
assign f = g36;
|
||||
assign g = g37;
|
||||
```
|
||||
|
||||
### simple-simplified version, with "normal" gates
|
||||
in this circuit, repeated OR operations were "abbreviated": 4-input OR gates were replaced by 3 2-input OR gates, taking advantage of the fact that many of those 2-input ORs are common and can be reused.
|
||||
|
||||
here the transformation to NOR gates is not as straightforward: each OR that is an input for another OR, has to be inverted (adding a NOT) before being able to convert OR, AND to NORs.
|
||||
|
||||
this circuit is implemented as one of the {coloring computers}.
|
||||
|
||||
=> ./img/dibujo_20201207_hex7segdecoder_small.png the complete decoder
|
||||
|
||||
``` verilog
|
||||
// 4-bit hexadecimal to 7-segment decoder with traditional gates, "simplified"
|
||||
module hex_to_7seg( b3, b2, b1, b0, a, b, c, d, e, f, g);
|
||||
|
||||
input wire b3, b2, b1, b0; // 4 bits as input
|
||||
output wire a, b, c, d, e, f, g; // 7 segments as output
|
||||
|
||||
// inversions:
|
||||
wire n3,n2,n1,n0;
|
||||
// maxterms:
|
||||
wire orD, orC, orB, orA, or9, or7, or5, or4, or2, or1;
|
||||
|
||||
// others:
|
||||
wire or111X, or11X0, or1X11, orX110, orX111, or010X, or00X1, or001X, or0X11, or000X;
|
||||
wire or0XX1;
|
||||
wire orXX00, orXX01, orXX10, orXX11, or00XX, or01XX, or10XX, or11XX;
|
||||
|
||||
wire and_or1or4, and_or111Xor11X0;
|
||||
|
||||
// inversions (4 gates)
|
||||
not N00( n0, b0);
|
||||
not N01( n1, b1);
|
||||
not N02( n2, b2);
|
||||
not N03( n3, b3);
|
||||
|
||||
// pairs of bits (9 gates)
|
||||
or P00( orXX00, b1, b0); // ++
|
||||
or P01( orXX01, b1, n0); // ++++
|
||||
or P02( orXX10, n1, b0); // +++
|
||||
or P03( orXX11, n1, n0); // ++++
|
||||
or P04( or00XX, b3, b2); // +++
|
||||
or P05( or01XX, b3, n2); // ++++
|
||||
or P06( or10XX, n3, b2); // +++
|
||||
or P07( or11XX, n3, n2); // ++++
|
||||
// 2-input OR:
|
||||
or P08( or0XX1, b3, n0); // ++
|
||||
|
||||
// was-3-input ORs (10 gates)
|
||||
or T00(or111X, or11XX, n1); //n3, n2, n1;
|
||||
or T01(or11X0, or11XX, b0); //n3, n2, b0;
|
||||
or T02(or1X11, orXX11, n3); //n3, n1, n0;
|
||||
or T03(orX110, orXX10, n2); //n2, n1, b0;
|
||||
or T04(orX111, orXX11, n2); //n2, n1, n0;
|
||||
or T05(or010X, or01XX, b1); //b3, n2, b1;
|
||||
or T06(or00X1, or0XX1, b2 ); //b3, b2, n0;
|
||||
or T07(or001X, or00XX, n1 ); //b3, b2, n1;
|
||||
or T08(or0X11, or0XX1, n1 ); //b3, n1, n0;
|
||||
or T09(or000X, or00XX, b1 ); //b3, b2, b1;
|
||||
|
||||
// maxterms: (10 gates, 2-input)
|
||||
// we keep the maxterms: 1, 2, 4, 5, 7, 9, A, B, C, D
|
||||
or M1( or1, or00XX, orXX01); // 0b0001, 1
|
||||
or M2( or2, or00XX, orXX10); // 0b0010, 2
|
||||
or M4( or4, or01XX, orXX00); // 0b0100, 4
|
||||
or M5( or5, or01XX, orXX01); // 0b0101, 5
|
||||
or M7( or7, or01XX, orXX11); // 0b0111, 7
|
||||
or M9( or9, or10XX, orXX01); // 0b1001, 9
|
||||
or MA( orA, or10XX, orXX10); // 0b1010, A
|
||||
or MB( orB, or10XX, orXX11); // 0b1011, B
|
||||
or MC( orC, or11XX, orXX00); // 0b1100, C
|
||||
or MD( orD, or11XX, orXX01); // 0b1101, D
|
||||
|
||||
// helper ANDs (2 gates, 2-inputs)
|
||||
and A01( and_or1or4, or1, or4);
|
||||
and A02( and_or111Xor11X0, or111X, or11X0);
|
||||
|
||||
// each segment (7 gates)
|
||||
and Sa( a, and_or1or4, orB, orD); // 3-inputs
|
||||
and Sb( b, and_or111Xor11X0, or1X11, orX110, or5); // 4-inputs
|
||||
and Sc( c, and_or111Xor11X0, or2); // 2-inputs
|
||||
and Sd( d, and_or1or4, orX111, orA); // 3-inputs
|
||||
and Se( e, or0XX1, or010X, or9); // 3-inputs
|
||||
and Sf( f, or00X1, or001X, or0X11, orD); // 4-inputs
|
||||
and Sg( g, or000X, or7, orC); // 3-inputs
|
||||
|
||||
endmodule
|
||||
```
|
||||
|
||||
# bouncing ball
|
||||
|
||||
see {bouncing ball logic}.
|
||||
|
|
@ -16,6 +16,7 @@ have around two types of beans, like black beans and soy beans, print out the PD
|
|||
|
||||
# download
|
||||
|
||||
+ <iframe frameborder="0" src="https://itch.io/embed/1365973" width="552" height="167"><a href="https://compudanzas.itch.io/norpet">norpet by compudanzas</a></iframe>
|
||||
=> https://compudanzas.itch.io/norpet download norpet from itch.io
|
||||
|
||||
# about
|
||||
|
|
|
|||
|
|
@ -16,6 +16,7 @@ ten cerca dos tipos de frijoles, como frijoles negros y frijoles de soya, imprim
|
|||
|
||||
# descarga
|
||||
|
||||
+ <iframe frameborder="0" src="https://itch.io/embed/1365973" width="552" height="167"><a href="https://compudanzas.itch.io/norpet">norpet by compudanzas</a></iframe>
|
||||
=> https://compudanzas.itch.io/norpet descarga norpet from itch.io
|
||||
|
||||
la traducción al español del tablero e instrucciones la realizó vladomiro, ¡muchas gracias!
|
||||
|
|
@ -23,7 +24,7 @@ la traducción al español del tablero e instrucciones la realizó vladomiro, ¡
|
|||
|
||||
# acerca de
|
||||
|
||||
norpet fue una prueba de concepto de computación con frijoles y en papel que desarrollamos para un Jam de mascotas virtuales en itch.io
|
||||
norpet fue una prueba de concepto de {cómputo frijol} y en papel que desarrollamos para un Jam de mascotas virtuales en itch.io
|
||||
|
||||
=> https://itch.io/jam/virtual-pet-jam Virtual Pet Jam - itch.io
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,23 @@
|
|||
# POÑG
|
||||
lang=en
|
||||
a human-scale digital videogame, with logic provided by people.
|
||||
|
||||
# the original idea
|
||||
|
||||
the following text is a slightly edited summary in english from around 12020-11 about {propuesta poñg}, originally written in spanish:
|
||||
|
||||
some time ago, i applied for a grant with this project: "a human-scale digital videogame, with logic provided by people". "a very low-res (16x12) monochromatic game simulating a tennis match between two people". i didn't get it, but i decided i'll design and build it nevertheles.
|
||||
|
||||
i consider this videogame is "electric" but not electronic: it uses electricity, wires, switches and LEDs/lightbulbs, but the logic is not semiconductor-based, it is human-based.
|
||||
|
||||
there are two human players with "controllers", but someone ("the operator(s)") has to go through each and every switch of the system, putting it in the corresponding position according to the (light) state of its inputs (a {nor} operation!), in order to calculate one frame.
|
||||
|
||||
when the frame is ready, it is "switched" into a display: players and audience can see the new state of the game, we can take an instant photography to document the frame, players can adjust the state of their controller, the display turns off and the switching process starts again.
|
||||
|
||||
the inputs of each iteration for the operator and the logic network would be a "vector" with the state of the game plus the state of the controllers.
|
||||
|
||||
# initial iteration
|
||||
|
||||
the initial iteration in 12020 resulted in some {beans computing} prototypes, which are documented in {bouncing ball logic} and {bouncer-2d prototype}.
|
||||
|
||||
=> ./img/secuencia_bounce2d-8x6-0a3.gif a sequence of four frames showing two paper boards with black and soy beans in them: the one in the left contains the processing cells, and the one in the right looks like a screen composed of soy beans except for one, which seems to be moving from the top left corner to the bottom and right.
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@ -1,5 +1,7 @@
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# POÑG (Propuesta)
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lang=es
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el origen de {poñg}.
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este texto fue enviado como parte de mi postulación para el programa jóvenes creadores (1)2020-(1)2021 del fonca, en la disciplina de medios audiovisuales, especialidad de nuevas tecnologías.
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la propuesta no fue aceptada en la fase resolutiva.
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Reference in New Issue