47 lines
1.1 KiB
Plaintext
47 lines
1.1 KiB
Plaintext
# Tool for simulating verilog
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EXEFILE_VSIM ?= iverilog
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# Path to bsim
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EXEFILE_VSIM ?= bsim
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all: compile link sim
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compile:
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@echo Compiling for Bluesim ...
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bsc -u -sim $(BSCDIRS_BSIM) $(BSCFLAGS) -p $(BSCPATH_BSIM) $(TOPFILE)
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@echo Compilation for Bluesim finished
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link:
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@echo Linking for Bluesim ...
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bsc -sim -parallel-sim-link 8\
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$(BSCDIRS_BSIM) -p $(BSCPATH_BSIM) \
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-e $(TOPMODULE) -o ./$(EXEFILE_BSIM) \
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-keep-fires \
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$(BSC_C_FLAGS)
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@echo Linking for Bluesim finished
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sim:
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@echo Simulation in Bluesim...
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./$(EXEFILE_BSIM)
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@echo Simulation in Bluesim finished
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vall: v_compile v_link v_sim
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v_compile: build_v verilog
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@echo "Compiling for Verilog (Verilog generation) ..."
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bsc -u -elab -verilog $(BSCDIRS_V) $(BSCFLAGS) -p $(BSCPATH_V) $(TOPFILE)
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@echo Verilog generation finished
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v_link:
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@echo Linking for Verilog simulation ...
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bsc -verilog -vsim $(VSIM) $(BSCDIRS_V) \
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-e $(TOPMODULE) -o ./$(EXEFILE_VSIM) \
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-keep-fires
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@echo Linking for Verilog simulation finished
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v_sim:
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@echo Verilog simulation ...
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./$(EXEFILE_VSIM)
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@echo Verilog simulation finished
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