H10 PP Crash -- Fixed
This appears to finally fix the issue turns out the status register we were writing was only for the CPU COP cache flush wiped out the CPU cache -- Added some defines to cut down on the magic numbers Added some comments explaining such Set the address to full 20 bit address 0x1FFFFF which is then left shifted 11 internally -- somewhere around 4GB? Link explains the cache status bits https://daniel.haxx.se/sansa/memory_controller.txt Change-Id: I57b7187c2f71a5b54ce145bf3a21ed492a8993cb
This commit is contained in:
William Wilgus
parent
058a9ec945
commit
89acde6af2
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@ -584,8 +584,10 @@
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#define CACHE_DATA_BASE (*(volatile unsigned long*)(0xf0000000))
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/* 0xf0002000-0xf0003fff */
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#define CACHE_DATA_MIRROR_BASE (*(volatile unsigned long*)(0xf0002000))
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/* 0xf0004000-0xf0007fff */
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#define CACHE_STATUS_BASE (*(volatile unsigned long*)(0xf0004000))
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/* 0xf0004000-0xf0005fff */
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#define CACHE_STATUS_BASE_CPU (*(volatile unsigned long*)(0xf0004000))
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/* 0xf0006000-0xf0007fff */
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#define CACHE_STATUS_BASE_COP (*(volatile unsigned long*)(0xf0006000))
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#define CACHE_FLUSH_BASE (*(volatile unsigned long*)(0xf0008000))
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#define CACHE_INVALID_BASE (*(volatile unsigned long*)(0xf000c000))
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#define MMAP_PHYS_READ_MASK 0x0100
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@ -29,6 +29,21 @@
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#include "button-target.h"
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#include "usb_drv.h"
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/* Bit 0 - 20: Cached Address */
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#define CACHE_ADDRESS_MASK ((1<<21)-1)
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/* Bit 22: Cache line dirty */
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#define CACHE_LINE_DIRTY (1<<22)
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/* Bit 23: Cache line valid */
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#define CACHE_LINE_VALID (1<<23)
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/* Cache Size - 8K*/
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#define CACHE_SIZE 0x2000
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/*Initial memory address used to prime cache
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* could be targeted to a more 'important' address
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* Note: Don't start at 0x0, as the compiler thinks it's a
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* null pointer dereference and will helpfully blow up the code. */
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#define CACHED_INIT_ADDR CACHEALIGN_UP(0x2000)
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#if !defined(BOOTLOADER) || defined(HAVE_BOOTLOADER_USB_MODE)
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extern void TIMER1(void);
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extern void TIMER2(void);
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@ -44,7 +59,7 @@ unsigned char probed_ramsize;
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void __attribute__((interrupt("IRQ"))) irq_handler(void)
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{
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if(CURRENT_CORE == CPU)
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if(IF_COP_CORE(CPU) == CPU)
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{
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if (CPU_INT_STAT & TIMER1_MASK) {
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TIMER1();
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@ -218,6 +233,39 @@ void ICODE_ATTR commit_dcache(void)
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}
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}
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static void ICODE_ATTR cache_invalidate_special(void)
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{
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/* Cache lines which are not marked as valid can cause memory
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* corruption when there are many writes to and code fetches from
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* cached memory. This workaround points all cache status to the
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* maximum line address and marked valid but not dirty. Since that area
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* is never accessed, the cache lines don't affect anything, and
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* they're effectively discarded. Interrupts must be disabled here
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* because any change they make to cached memory could be discarded.
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* A status word is 32 bits and is mirrored four times for each cache line
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bit 0-20 line_address >> 11
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bit 21 unused?
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bit 22 line_dirty
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bit 23 line_valid
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bit 24-31 unused?
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*/
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register volatile unsigned long *p;
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if (IF_COP_CORE(CPU) == CPU)
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{
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for (p = &CACHE_STATUS_BASE_CPU;
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p < (&CACHE_STATUS_BASE_CPU) + CACHE_SIZE;
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p += CACHEALIGN_BITS) /* sizeof(p) * CACHEALIGN_BITS */
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*p = CACHE_LINE_VALID | CACHE_ADDRESS_MASK;
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}
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else
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{
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for (p = &CACHE_STATUS_BASE_COP;
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p < (&CACHE_STATUS_BASE_COP) + CACHE_SIZE;
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p += CACHEALIGN_BITS)
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*p = CACHE_LINE_VALID | CACHE_ADDRESS_MASK;
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}
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}
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void ICODE_ATTR commit_discard_idcache(void)
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{
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if (CACHE_CTL & CACHE_CTL_ENABLE)
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@ -225,21 +273,7 @@ void ICODE_ATTR commit_discard_idcache(void)
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register int istat = disable_interrupt_save(IRQ_FIQ_STATUS);
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commit_dcache();
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/* Cache lines which are not marked as valid can cause memory
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* corruption when there are many writes to and code fetches from
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* cached memory. This workaround points all cache status words past
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* end of RAM and marks them as valid, but not dirty. Since that area
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* is never accessed, the cache lines don't affect anything, and
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* they're effectively discarded. Interrupts must be disabled here
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* because any change they make to cached memory could be discarded.
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*/
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register volatile unsigned long *p;
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for (p = &CACHE_STATUS_BASE;
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p < (&CACHE_STATUS_BASE) + 512*16/sizeof(*p);
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p += 16/sizeof(*p))
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*p = ((MEMORYSIZE*0x100000) >> 11) | 0x800000;
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cache_invalidate_special();
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restore_interrupt(istat);
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}
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@ -258,7 +292,7 @@ static void init_cache(void)
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#ifndef BOOTLOADER
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/* what's this do? */
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CACHE_PRIORITY |= CURRENT_CORE == CPU ? 0x10 : 0x20;
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CACHE_PRIORITY |= IF_COP_CORE(CPU) == CPU ? 0x10 : 0x20;
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#endif
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/* Cache if (addr & mask) >> 16 == (mask & match) >> 16:
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@ -278,11 +312,8 @@ static void init_cache(void)
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* can run from cached RAM, rewriting of cache status words may not
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* be safe and the cache is filled instead by reading. */
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/* Note: Don't start at 0x0, as the compiler thinks it's a
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null pointer dereference and will helpfully blow up the code. */
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register volatile char *p;
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for (p = (volatile char *)0x1000; p < (volatile char *)0x3000; p += 0x10)
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register volatile char *p = (volatile char *)CACHED_INIT_ADDR;
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for (;p < (volatile char *)CACHED_INIT_ADDR + CACHE_SIZE; p += CACHEALIGN_SIZE)
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(void)*p;
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}
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#endif /* BOOTLOADER || HAVE_BOOTLOADER_USB_MODE */
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@ -293,7 +324,7 @@ static void init_cache(void)
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void scale_suspend_core(bool suspend) ICODE_ATTR;
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void scale_suspend_core(bool suspend)
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{
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unsigned int core = CURRENT_CORE;
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unsigned int core = IF_COP_CORE(CPU);
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IF_COP( unsigned int othercore = 1 - core; )
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static int oldstatus IBSS_ATTR;
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@ -442,7 +473,7 @@ static void pp_set_cpu_frequency(long frequency)
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#ifndef BOOTLOADER
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void system_init(void)
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{
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if (CURRENT_CORE == CPU)
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if (IF_COP_CORE(CPU) == CPU)
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{
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#if defined (IRIVER_H10) || defined(IRIVER_H10_5GB) || defined(IPOD_COLOR)
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/* set minimum startup configuration */
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@ -628,7 +659,7 @@ void system_exception_wait(void)
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COP_INT_DIS = -1;
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/* Halt */
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PROC_CTL(CURRENT_CORE) = 0x40000000;
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PROC_CTL(IF_COP_CORE(CPU)) = 0x40000000;
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while (1);
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}
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