Sansa AMS: Use DMA for SD transfers (read and write)
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@19211 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Rafaël Carré
parent
d7e4e54bcb
commit
c1f90b1881
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@ -343,6 +343,7 @@ target/arm/as3525/kernel-as3525.c
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target/arm/as3525/ata_sd_as3525.c
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target/arm/as3525/power-as3525.c
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target/arm/as3525/usb-as3525.c
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target/arm/as3525/dma-pl081.c
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#ifndef BOOTLOADER
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target/arm/adc-as3514.c
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target/arm/as3525/pcm-as3525.c
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@ -0,0 +1,77 @@
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/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright © 2008 Rafaël Carré
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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/* Note: since the base address is not specified, you need to define DMAC_BASE
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* before including this file */
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/* ARM PrimeCell PL081 Single Master DMA controller */
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#define DMAC_INT_STATUS (*(volatile unsigned long*)(DMAC_BASE+0x000))
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#define DMAC_INT_TC_STATUS (*(volatile unsigned long*)(DMAC_BASE+0x004))
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#define DMAC_INT_TC_CLEAR (*(volatile unsigned long*)(DMAC_BASE+0x008))
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#define DMAC_INT_ERROR_STATUS (*(volatile unsigned long*)(DMAC_BASE+0x00C))
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#define DMAC_INT_ERR_CLEAR (*(volatile unsigned long*)(DMAC_BASE+0x010))
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#define DMAC_RAW_INT_TC_STATUS (*(volatile unsigned long*)(DMAC_BASE+0x014))
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#define DMAC_RAW_INT_ERROR_STATUS (*(volatile unsigned long*)(DMAC_BASE+0x018))
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#define DMAC_ENBLD_CHANS (*(volatile unsigned long*)(DMAC_BASE+0x01C))
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#define DMAC_SOFT_B_REQ (*(volatile unsigned long*)(DMAC_BASE+0x020))
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#define DMAC_SOFT_S_REQ (*(volatile unsigned long*)(DMAC_BASE+0x024))
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#define DMAC_SOFT_LB_REQ (*(volatile unsigned long*)(DMAC_BASE+0x028))
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#define DMAC_SOFT_LS_REQ (*(volatile unsigned long*)(DMAC_BASE+0x02C))
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#define DMAC_CONFIGURATION (*(volatile unsigned long*)(DMAC_BASE+0x030))
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#define DMAC_SYNC (*(volatile unsigned long*)(DMAC_BASE+0x034))
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/* Channel registers (0 & 1) */
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#define DMAC_CH_SRC_ADDR(c) (*(volatile unsigned long*)(DMAC_BASE+0x100+(0x20*c)))
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#define DMAC_CH_DST_ADDR(c) (*(volatile unsigned long*)(DMAC_BASE+0x104+(0x20*c)))
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#define DMAC_CH_LLI(c) (*(volatile unsigned long*)(DMAC_BASE+0x108+(0x20*c)))
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#define DMAC_CH_CONTROL(c) (*(volatile unsigned long*)(DMAC_BASE+0x10C+(0x20*c)))
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#define DMAC_CH_CONFIGURATION(c) (*(volatile unsigned long*)(DMAC_BASE+0x110+(0x20*c)))
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/* Test registers */
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#define DMAC_ITCR (*(volatile unsigned long*)(DMAC_BASE+0x500))
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#define DMAC_ITOP1 (*(volatile unsigned long*)(DMAC_BASE+0x504))
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#define DMAC_ITOP2 (*(volatile unsigned long*)(DMAC_BASE+0x508))
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#define DMAC_ITOP3 (*(volatile unsigned long*)(DMAC_BASE+0x50C))
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/* Flow controllers */
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/* Controller is DMAC */
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#define DMAC_FLOWCTRL_DMAC_MEM_TO_MEM 0
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#define DMAC_FLOWCTRL_DMAC_MEM_TO_PERI 1
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#define DMAC_FLOWCTRL_DMAC_PERI_TO_MEM 2
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#define DMAC_FLOWCTRL_DMAC_PERI_TO_PERI 3
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/* Controller is peripheral */
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#define DMAC_FLOWCTRL_SRC_PERI_PERI_TO_PERI 4
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#define DMAC_FLOWCTRL_PERI_MEM_TO_PERI 5
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#define DMAC_FLOWCTRL_PERI_PERI_TO_MEM 6
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#define DMAC_FLOWCTRL_DST_PERI_PERI_TO_PERI 7
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/* Transfer request sizes */
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#define DMA_S1 0
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#define DMA_S4 1
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#define DMA_S8 2
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#define DMA_S16 3
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#define DMA_S32 4
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#define DMA_S64 5
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#define DMA_S128 6
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#define DMA_S256 7
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@ -32,7 +32,9 @@
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#include <stdlib.h>
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#include <string.h>
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#include "as3525.h"
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#include "pl180.h"
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#include "pl180.h" /* SD controller */
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#include "pl081.h" /* DMA controller */
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#include "dma-target.h" /* DMA request lines */
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#include "panic.h"
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#include "stdbool.h"
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#include "ata_idle_notify.h"
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@ -71,8 +73,8 @@
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#define MCI_FIFO(i) ((unsigned long *) (pl180_base[i]+0x80))
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/* volumes */
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#define NAND_AS3525 0 /* embedded SD card */
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#define SD_AS3525 1 /* SD slot if present */
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#define INTERNAL_AS3525 0 /* embedded SD card */
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#define SD_SLOT_AS3525 1 /* SD slot if present */
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static const int pl180_base[NUM_VOLUMES] = {
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NAND_FLASH_BASE
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@ -81,6 +83,7 @@ static const int pl180_base[NUM_VOLUMES] = {
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#endif
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};
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/* TODO : BLOCK_SIZE != SECTOR_SIZE ? */
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#define BLOCK_SIZE 512
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#define SECTOR_SIZE 512
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@ -389,8 +392,8 @@ int sd_init(void)
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CGU_PERI |= CGU_MCI_CLOCK_ENABLE;
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#endif
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init_pl180_controller(NAND_AS3525);
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ret = sd_init_card(NAND_AS3525);
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init_pl180_controller(INTERNAL_AS3525);
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ret = sd_init_card(INTERNAL_AS3525);
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if(ret < 0)
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return ret;
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@ -398,8 +401,8 @@ int sd_init(void)
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CCU_IO &= ~8; /* bits 3:2 = 01, xpd is SD interface */
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CCU_IO |= 4;
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init_pl180_controller(SD_AS3525);
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sd_init_card(SD_AS3525);
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init_pl180_controller(SD_SLOT_AS3525);
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sd_init_card(SD_SLOT_AS3525);
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#endif
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queue_init(&sd_queue, true);
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@ -441,40 +444,6 @@ bool sd_present(IF_MV_NONVOID(int drive))
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}
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#endif
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int sd_write_sectors(IF_MV2(int drive,) unsigned long start, int count, const void* buf)
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{
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(void)start;
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(void)count;
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(void)buf;
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return -1; /* TODO */
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}
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static int sd_poll_status(const int drive, unsigned int trigger, long timeout)
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{
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long t = current_tick;
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//int my_next_yield =0;
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int status;
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while (((status = MCI_STATUS(drive)) & trigger) == 0)
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{
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long time = current_tick;
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/*
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if (TIME_AFTER(time, my_next_yield))
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{
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long ty = current_tick;
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yield();
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timeout += current_tick - ty;
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my_next_yield = ty + MIN_YIELD_PERIOD;
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}
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*/
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if (TIME_AFTER(time, t + timeout))
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break;
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}
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return status;
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}
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static int sd_wait_for_state(const int drive, unsigned int state)
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{
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unsigned int response = 0;
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@ -484,7 +453,7 @@ static int sd_wait_for_state(const int drive, unsigned int state)
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while (1)
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{
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long us;
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long tick;
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if(!send_cmd(drive, SD_SEND_STATUS, card_info[drive].rca,
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MCI_RESP|MCI_ARG, &response))
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@ -496,35 +465,30 @@ static int sd_wait_for_state(const int drive, unsigned int state)
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if(TIME_AFTER(current_tick, t + timeout))
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return -1;
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us = current_tick;
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if (TIME_AFTER(us, next_yield))
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if (TIME_AFTER((tick = current_tick), next_yield))
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{
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yield();
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timeout += current_tick - us;
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next_yield = us + MIN_YIELD_PERIOD;
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timeout += current_tick - tick;
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next_yield = tick + MIN_YIELD_PERIOD;
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}
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}
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}
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int sd_read_sectors(IF_MV2(int drive,) unsigned long start, int incount,
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void* inbuf)
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static int sd_transfer_sectors(IF_MV2(int drive,) unsigned long start,
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int count, void* buf, bool write)
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{
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#ifndef HAVE_MULTIVOLUME
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const int drive = 0;
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#endif
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int ret;
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unsigned char *buf_end, *buf = inbuf;
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int remaining = incount;
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const unsigned long *fifo_base = MCI_FIFO(drive);
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/* skip SanDisk OF */
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if (drive == NAND_AS3525)
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if (drive == INTERNAL_AS3525)
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#if defined(SANSA_E200V2) || defined(SANSA_FUZE)
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start += 61440;
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#else
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start += 20480;
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#endif
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/* TODO: Add DMA support. */
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mutex_lock(&sd_mtx);
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@ -533,15 +497,15 @@ int sd_read_sectors(IF_MV2(int drive,) unsigned long start, int incount,
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{
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/* no external sd-card inserted */
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ret = -88;
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goto sd_read_error;
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goto sd_transfer_error;
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}
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#endif
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if (card_info[drive].initialized < 0)
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{
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ret = card_info[drive].initialized;
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panicf("card not initalised");
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goto sd_read_error;
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panicf("card not initialised");
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goto sd_transfer_error;
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}
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last_disk_activity = current_tick;
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@ -550,109 +514,103 @@ int sd_read_sectors(IF_MV2(int drive,) unsigned long start, int incount,
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if (ret < 0)
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{
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panicf("wait for state failed");
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goto sd_read_error;
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goto sd_transfer_error;
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}
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disable_irq(); /* FIXME: data transfer is too slow and error prone when
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* interrupts are enabled */
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while(remaining)
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while(count)
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{
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/* 128 * 512 = 2^16, and doesn't fit in the 16 bits of DATA_LENGTH
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* register, so we have to transfer maximum 127 sectors at a time. */
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int transfer = (remaining >= 128) ? 127 : remaining; /* sectors */
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unsigned int transfer = (count >= 128) ? 127 : count; /* sectors */
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const int cmd =
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write ? SD_WRITE_MULTIPLE_BLOCK : SD_READ_MULTIPLE_BLOCK;
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if(card_info[drive].ocr & (1<<30) ) /* SDHC */
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ret = send_cmd(drive, SD_READ_MULTIPLE_BLOCK, start, MCI_ARG, NULL);
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ret = send_cmd(drive, cmd, start, MCI_ARG, NULL);
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else
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ret = send_cmd(drive, SD_READ_MULTIPLE_BLOCK, start * BLOCK_SIZE,
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ret = send_cmd(drive, cmd, start * BLOCK_SIZE,
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MCI_ARG, NULL);
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if (ret < 0)
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{
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panicf("read multiple blocks failed");
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goto sd_read_error;
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panicf("transfer multiple blocks failed");
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goto sd_transfer_error;
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}
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/* TODO: Don't assume BLOCK_SIZE == SECTOR_SIZE */
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if(write)
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dma_enable_channel(0, buf, MCI_FIFO(drive),
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(drive == INTERNAL_AS3525) ? DMA_PERI_SD : DMA_PERI_SD_SLOT,
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DMAC_FLOWCTRL_PERI_MEM_TO_PERI, true, false, 0, DMA_S8);
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else
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dma_enable_channel(0, MCI_FIFO(drive), buf,
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(drive == INTERNAL_AS3525) ? DMA_PERI_SD : DMA_PERI_SD_SLOT,
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DMAC_FLOWCTRL_PERI_PERI_TO_MEM, false, true, 0, DMA_S8);
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MCI_DATA_TIMER(drive) = 0x1000000; /* FIXME: arbitrary */
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MCI_DATA_LENGTH(drive) = transfer * card_info[drive].block_size;
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MCI_DATA_CTRL(drive) = (1<<0) /* enable */ |
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(1<<1) /* from card to controller */ |
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MCI_DATA_CTRL(drive) = (1<<0) /* enable */ |
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(!write<<1) /* transfer direction */ |
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(1<<3) /* DMA */ |
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(9<<4) /* 2^9 = 512 */ ;
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buf_end = buf + transfer * card_info[drive].block_size;
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while(!dma_finished)
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yield();
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while(buf < buf_end)
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{
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/* Wait for the FIFO to be half full */
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const int trigger = MCI_RX_FIFO_HALF_FULL|MCI_RX_FIFO_FULL;
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int controller_status = sd_poll_status(drive, trigger, 100);
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controller_status &= ~(MCI_RX_ACTIVE|MCI_RX_DATA_AVAIL|
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MCI_DATA_BLOCK_END|MCI_DATA_END);
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if(!controller_status || (controller_status & ~trigger))
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panicf("incorrect status 0x%x", controller_status & ~trigger);
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if(((intptr_t)buf & 3) == 0)
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{ /* aligned destination buffer */
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asm volatile(
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"ldmia %2, {r0-r7} \n" /* load 8 * 4 bytes */
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"stmia %1!, {r0-r7} \n" /* store 8 * 4 bytes */
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:"=r"(buf) /* output */
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:"r"(buf), "r"(fifo_base) /* input */
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:"r0","r1","r2","r3","r4","r5","r6","r7" /* clobbers */
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);
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}
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else
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{ /* non aligned destination buffer */
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int tmp[8];
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asm volatile(
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"ldmia %1, {r0-r7} \n" /* load 8 * 4 bytes */
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"stmia %0, {r0-r7} \n" /* store 8 * 4 bytes */
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:/* no output */
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:"r"(tmp), "r"(fifo_base) /* input */
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:"r0","r1","r2","r3","r4","r5","r6","r7" /* clobbers */
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);
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memcpy(buf, tmp, 32);
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buf = &buf[32];
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}
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}
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remaining -= transfer;
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buf += transfer * SECTOR_SIZE;
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start += transfer;
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count -= transfer;
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last_disk_activity = current_tick;
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if(!send_cmd(drive, SD_STOP_TRANSMISSION, 0, MCI_NO_FLAGS, NULL))
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{
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ret = -666;
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panicf("STOP TRANSMISSION failed");
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goto sd_read_error;
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goto sd_transfer_error;
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}
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ret = sd_wait_for_state(drive, SD_TRAN);
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if (ret < 0)
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{
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panicf(" wait for state TRAN failed");
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goto sd_read_error;
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goto sd_transfer_error;
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}
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}
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while (1)
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{
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mutex_unlock(&sd_mtx);
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enable_irq();
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return ret;
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sd_read_error:
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panicf("read error : %d",ret);
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sd_transfer_error:
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panicf("transfer error : %d",ret);
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card_info[drive].initialized = 0;
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}
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}
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int sd_read_sectors(IF_MV2(int drive,) unsigned long start, int count,
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void* buf)
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{
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return sd_transfer_sectors(IF_MV2(drive,) start, count, buf, false);
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}
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int sd_write_sectors(IF_MV2(int drive,) unsigned long start, int count,
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const void* buf)
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{
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#ifdef BOOTLOADER /* we don't need write support in bootloader */
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#ifdef HAVE_MULTIVOLUME
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(void) drive;
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#endif
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(void) start;
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(void) count;
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(void) buf;
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return -1;
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#else
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return sd_transfer_sectors(IF_MV2(drive,) start, count, (void*)buf, true);
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#endif
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}
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#ifndef BOOTLOADER
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void sd_sleep(void)
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{
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@ -0,0 +1,96 @@
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/***************************************************************************
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* __________ __ ___.
|
||||
* Open \______ \ ____ ____ | | _\_ |__ _______ ___
|
||||
* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
|
||||
* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
|
||||
* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
|
||||
* \/ \/ \/ \/ \/
|
||||
* $Id$
|
||||
*
|
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* Copyright © 2008 Rafaël Carré
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*
|
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* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
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* as published by the Free Software Foundation; either version 2
|
||||
* of the License, or (at your option) any later version.
|
||||
*
|
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
|
||||
* KIND, either express or implied.
|
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*
|
||||
****************************************************************************/
|
||||
|
||||
#include "as3525.h"
|
||||
#include "pl081.h"
|
||||
#include "dma-target.h"
|
||||
#include <stdbool.h>
|
||||
#include "panic.h"
|
||||
|
||||
volatile bool dma_finished;
|
||||
|
||||
void dma_init(void)
|
||||
{
|
||||
/* Enable DMA controller */
|
||||
CGU_PERI |= CGU_DMA_CLOCK_ENABLE;
|
||||
DMAC_CONFIGURATION |= (1<<0);
|
||||
DMAC_SYNC = 0;
|
||||
VIC_INT_ENABLE |= INTERRUPT_DMAC;
|
||||
}
|
||||
|
||||
void dma_enable_channel(int channel, void *src, void *dst, int peri,
|
||||
int flow_controller, bool src_inc, bool dst_inc,
|
||||
size_t size, int nwords)
|
||||
{
|
||||
int control = 0;
|
||||
|
||||
DMAC_CH_SRC_ADDR(channel) = (int)src;
|
||||
DMAC_CH_DST_ADDR(channel) = (int)dst;
|
||||
|
||||
DMAC_CH_LLI(channel) = 0; /* we use contigous memory, so don't use the LLI */
|
||||
|
||||
/* specify address increment */
|
||||
if(src_inc)
|
||||
control |= (1<<26);
|
||||
|
||||
if(dst_inc)
|
||||
control |= (1<<27);
|
||||
|
||||
/* OF use transfers of 4 * 32 bits words on memory, i2sin, i2sout */
|
||||
/* OF use transfers of 8 * 32 bits words on SD */
|
||||
|
||||
control |= (2<<21) | (2<<18); /* dst/src width = word, 32bit */
|
||||
control |= (nwords<<15) | (nwords<<12); /* dst/src size */
|
||||
control |= (size & 0x7ff); /* transfer size */
|
||||
|
||||
control |= (1<<31); /* current LLI is expected to trigger terminal count interrupt */
|
||||
|
||||
DMAC_CH_CONTROL(channel) = control;
|
||||
|
||||
dma_finished = false;
|
||||
|
||||
/* only needed if DMAC and Peripheral do not run at the same clock speed */
|
||||
DMAC_SYNC |= (1<<peri);
|
||||
|
||||
/* we set the same peripheral as source and destination because we always
|
||||
* use memory-to-peripheral or peripheral-to-memory transfers */
|
||||
DMAC_CH_CONFIGURATION(channel) =
|
||||
(flow_controller<<11) /* flow controller is peripheral */
|
||||
| (1<<15) /* terminal count interrupt mask */
|
||||
| (1<<14) /* interrupt error mask */
|
||||
| (peri<<6) /* dst peripheral */
|
||||
| (peri<<1) /* src peripheral */
|
||||
| (1<<0) /* enable channel */
|
||||
;
|
||||
}
|
||||
|
||||
/* isr */
|
||||
void INT_DMAC(void)
|
||||
{
|
||||
int channel = (DMAC_INT_STATUS & (1<<0)) ? 0 : 1;
|
||||
|
||||
if(DMAC_INT_ERROR_STATUS & (1<<channel))
|
||||
panicf("DMA error, channel %d", channel);
|
||||
|
||||
DMAC_INT_TC_CLEAR |= (1<<channel); /* clear terminal count interrupt */
|
||||
|
||||
dma_finished = true; /* TODO : use struct wakeup ? */
|
||||
}
|
||||
|
|
@ -0,0 +1,39 @@
|
|||
/***************************************************************************
|
||||
* __________ __ ___.
|
||||
* Open \______ \ ____ ____ | | _\_ |__ _______ ___
|
||||
* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
|
||||
* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
|
||||
* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
|
||||
* \/ \/ \/ \/ \/
|
||||
* $Id$
|
||||
*
|
||||
* Copyright © 2008 Rafaël Carré
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation; either version 2
|
||||
* of the License, or (at your option) any later version.
|
||||
*
|
||||
* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
|
||||
* KIND, either express or implied.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#include <stdbool.h>
|
||||
#include <stdlib.h>
|
||||
|
||||
/* DMA request lines (16 max): not specified in AS3525 datasheet, but common to
|
||||
* all AS3525 based models (made by SanDisk) supported by rockbox. */
|
||||
|
||||
#define DMA_PERI_SD_SLOT 2
|
||||
#define DMA_PERI_I2SOUT 3
|
||||
#define DMA_PERI_I2SIN 4
|
||||
#define DMA_PERI_SD 5 /* embedded storage */
|
||||
#define DMA_PERI_DBOP 8
|
||||
|
||||
void dma_init(void);
|
||||
void dma_enable_channel(int channel, void *src, void *dst, int peri,
|
||||
int flow_controller, bool src_inc, bool dst_inc,
|
||||
size_t size, int nwords);
|
||||
|
||||
extern volatile bool dma_finished;
|
||||
|
|
@ -24,6 +24,7 @@
|
|||
#include "system.h"
|
||||
#include "panic.h"
|
||||
#include "ascodec-target.h"
|
||||
#include "dma-target.h"
|
||||
|
||||
#define default_interrupt(name) \
|
||||
extern __attribute__((weak,alias("UIRQ"))) void name (void)
|
||||
|
|
@ -174,7 +175,7 @@ static void sdram_init(void)
|
|||
#elif defined(SANSA_E200V2) || defined(SANSA_FUZE)
|
||||
/* 16 bits external bus, high performance SDRAM, 64 Mbits = 8 Mbytes */
|
||||
#define MEMORY_MODEL 0x5
|
||||
|
||||
|
||||
#else
|
||||
#error "The external memory in your player is unknown"
|
||||
#endif
|
||||
|
|
@ -220,9 +221,6 @@ void system_init(void)
|
|||
CGU_PROC = (3<<2)|0x01; /* fclk = PLLA*5/8 = 240 MHz */
|
||||
|
||||
asm volatile(
|
||||
"mrs r0, cpsr \n"
|
||||
"orr r0, r0, #0x80 \n" /* disable interrupts */
|
||||
"msr cpsr, r0 \n"
|
||||
"mov r0, #0 \n"
|
||||
"mcr p15, 0, r0, c7, c7 \n" /* invalidate icache & dcache */
|
||||
"mrc p15, 0, r0, c1, c0 \n" /* control register */
|
||||
|
|
@ -239,15 +237,20 @@ void system_init(void)
|
|||
CGU_PERI |= CGU_TIMERIF_CLOCK_ENABLE;
|
||||
|
||||
/* enable VIC */
|
||||
VIC_INT_ENABLE = 0; /* disable all interrupt lines */
|
||||
CGU_PERI |= CGU_VIC_CLOCK_ENABLE;
|
||||
VIC_INT_SELECT = 0; /* only IRQ, no FIQ */
|
||||
|
||||
enable_irq();
|
||||
#else
|
||||
/* disable fast hardware power-off, to use power button normally */
|
||||
/* Disable fast hardware power-off, to use power button normally
|
||||
* We don't need the power button in the bootloader. */
|
||||
ascodec_init();
|
||||
ascodec_write(AS3514_CVDD_DCDC3, ascodec_read(AS3514_CVDD_DCDC3) & (1<<2));
|
||||
|
||||
#endif /* BOOTLOADER */
|
||||
|
||||
dma_init();
|
||||
}
|
||||
|
||||
void system_reboot(void)
|
||||
|
|
|
|||
Loading…
Reference in New Issue