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Improve ATA reset

This commit is contained in:
Vincent Ollivier 2020-07-12 09:55:05 +02:00
parent c4daf3a88c
commit da83646738
1 changed files with 8 additions and 7 deletions
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15
src/kernel/ata.rs
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@ -72,17 +72,18 @@ impl Bus {
fn reset(&mut self) {
unsafe {
self.control_register.write(4);
self.control_register.write(0);
self.control_register.write(4); // Set SRST bit
self.alternate_status_register.read(); // Wait at least 5 us
self.control_register.write(0); // Then clear it
for _ in 0..5 { // Wait at least 2 ms
self.wait();
}
}
}
fn wait(&mut self) {
unsafe {
self.alternate_status_register.read();
self.alternate_status_register.read();
self.alternate_status_register.read();
self.alternate_status_register.read();
for _ in 0..4 { // Wait about 4 x 100 ns
unsafe { self.alternate_status_register.read(); }
}
}