mirror of https://github.com/vinc/moros.git
451 lines
15 KiB
Rust
451 lines
15 KiB
Rust
use crate::sys;
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use crate::sys::allocator::PhysBuf;
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use crate::sys::net::{EthernetDeviceIO, Config, Stats};
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use spin::Mutex;
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use alloc::slice;
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use alloc::sync::Arc;
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use alloc::vec::Vec;
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use bit_field::BitField;
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use core::ptr;
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use core::sync::atomic::{AtomicUsize, Ordering};
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use smoltcp::wire::EthernetAddress;
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use x86_64::instructions::port::Port;
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use x86_64::PhysAddr;
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// https://pdos.csail.mit.edu/6.828/2019/readings/hardware/8254x_GBe_SDM.pdf
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// Registers
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const REG_CTRL: u16 = 0x0000; // Device Control Register
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const REG_STATUS: u16 = 0x0008; // Device Status Register
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const REG_EECD: u16 = 0x0014; // EEPROM/Flash Control & Data Register
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const REG_ICR: u16 = 0x00C0; // Interrupt Cause Read Register
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const REG_IMS: u16 = 0x00D0; // Interrupt Mask Set/Read Register
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const REG_IMC: u16 = 0x00D8; // Interrupt Mask Clear Register
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const REG_RCTL: u16 = 0x0100; // Receive Control Register
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const REG_RDBAL: u16 = 0x2800; // Receive Descriptor Base Address Low
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const REG_RDBAH: u16 = 0x2804; // Receive Descriptor Base Address High
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const REG_RDLEN: u16 = 0x2808; // Receive Descriptor Length
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const REG_RDH: u16 = 0x2810; // Receive Descriptor Head
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const REG_RDT: u16 = 0x2818; // Receive Descriptor Tail
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const REG_TCTL: u16 = 0x0400; // Transmit Control Register
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const REG_TIPG: u16 = 0x0410; // Transmit IPG Register
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const REG_TDBAL: u16 = 0x3800; // Transmit Descriptor Base Address Low
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const REG_TDBAH: u16 = 0x3804; // Transmit Descriptor Base Address High
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const REG_TDLEN: u16 = 0x3808; // Transmit Descriptor Length
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const REG_TDH: u16 = 0x3810; // Transmit Descriptor Head
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const REG_TDT: u16 = 0x3818; // Transmit Descriptor Tail
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const REG_MTA: u16 = 0x5200; // Multicast Table Array
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const CTRL_LRST: u32 = 1 << 3; // Link Reset
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const CTRL_ASDE: u32 = 1 << 5; // Auto-Speed Detection Enable
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const CTRL_SLU: u32 = 1 << 6; // Set Link Up
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const CTRL_RST: u32 = 1 << 26; // Reset
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const ICR_LSC: u32 = 1 << 2; // Link Status Change
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const ICR_RXDMT0: u32 = 1 << 4; // Receive Descriptor Minimum Threshold Reached
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const ICR_RXT0: u32 = 1 << 7; // Receiver Timer Interrupt
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const RCTL_EN: u32 = 1 << 1; // Receiver Enable
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const RCTL_BAM: u32 = 1 << 15; // Broadcast Accept Mode
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const RCTL_SECRC: u32 = 1 << 26; // Strip Ethernet CRC
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// Buffer Sizes
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// const RCTL_BSIZE_256: u32 = 3 << 16;
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// const RCTL_BSIZE_512: u32 = 2 << 16;
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// const RCTL_BSIZE_1024: u32 = 1 << 16;
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// const RCTL_BSIZE_2048: u32 = 0 << 16;
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// const RCTL_BSIZE_4096: u32 = (3 << 16) | (1 << 25);
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// const RCTL_BSIZE_16384: u32 = (1 << 16) | (1 << 25);
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const RCTL_BSIZE_8192: u32 = (2 << 16) | (1 << 25);
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const CMD_EOP: u8 = 1 << 0; // End of Packet
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const CMD_IFCS: u8 = 1 << 1; // Insert FCS
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const CMD_RS: u8 = 1 << 3; // Report Status
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const TCTL_EN: u32 = 1 << 1; // Transmit Enable
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const TCTL_PSP: u32 = 1 << 3; // Pad Short Packets
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const TCTL_MULR: u32 = 1 << 28; // Multiple Request Support
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const TCTL_CT_SHIFT: u32 = 4; // Collision Threshold
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const TCTL_COLD_SHIFT: u32 = 12; // Collision Distance
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// Transmit Descriptor Status Field
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const TSTA_DD: u8 = 1 << 0; // Descriptor Done
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// Receive Descriptor Status Field
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const RSTA_DD: u8 = 1 << 0; // Descriptor Done
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const RSTA_EOP: u8 = 1 << 1; // End of Packet
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// Device Status Register
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const DSTA_LU: u32 = 1 << 1; // Link Up Indication
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// Transmit IPG Register
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const TIPG_IPGT: u32 = 10; // IPG Transmit Time
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const TIPG_IPGR1: u32 = 8; // IPG Receive Time 1
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const TIPG_IPGR2: u32 = 6; // IPG Receive Time 2
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const IO_ADDR: u16 = 0x00;
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const IO_DATA: u16 = 0x04;
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// NOTE: Must be a multiple of 8
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const RX_BUFFERS_COUNT: usize = 64;
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const TX_BUFFERS_COUNT: usize = 8;
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// NOTE: Must be equals
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const BUFFER_SIZE: usize = 8192;
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const RCTL_BSIZE: u32 = RCTL_BSIZE_8192;
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#[derive(Clone, Copy, Debug, Default)]
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#[repr(C, align(16))]
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struct RxDesc {
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addr: u64,
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len: u16,
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checksum: u16,
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status: u8,
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errors: u8,
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special: u16,
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}
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#[derive(Clone, Copy, Debug, Default)]
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#[repr(C, align(16))]
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struct TxDesc {
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addr: u64,
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len: u16,
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cso: u8,
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cmd: u8,
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status: u8,
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css: u8,
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special: u16,
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}
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#[derive(Clone)]
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pub struct Device {
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mem_base: PhysAddr,
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io_base: u16,
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bar_type: u16,
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has_eeprom: bool,
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config: Arc<Config>,
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stats: Arc<Stats>,
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rx_buffers: [PhysBuf; RX_BUFFERS_COUNT],
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tx_buffers: [PhysBuf; TX_BUFFERS_COUNT],
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rx_descs: Arc<Mutex<[RxDesc; RX_BUFFERS_COUNT]>>,
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tx_descs: Arc<Mutex<[TxDesc; TX_BUFFERS_COUNT]>>,
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rx_id: Arc<AtomicUsize>,
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tx_id: Arc<AtomicUsize>,
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}
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impl Device {
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pub fn new(io_base: u16, mem_base: PhysAddr, bar_type: u16) -> Self {
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const RX: usize = RX_BUFFERS_COUNT;
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const TX: usize = TX_BUFFERS_COUNT;
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let mut device = Self {
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bar_type: bar_type,
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io_base: io_base,
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mem_base: mem_base,
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has_eeprom: false,
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config: Arc::new(Config::new()),
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stats: Arc::new(Stats::new()),
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rx_buffers: [(); RX].map(|_| PhysBuf::new(BUFFER_SIZE)),
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tx_buffers: [(); TX].map(|_| PhysBuf::new(BUFFER_SIZE)),
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rx_descs: Arc::new(Mutex::new([(); RX].map(|_| RxDesc::default()))),
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tx_descs: Arc::new(Mutex::new([(); TX].map(|_| TxDesc::default()))),
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rx_id: Arc::new(AtomicUsize::new(0)),
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// Before a transmission begin the id is incremented,
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// so the first transimission will start at 0.
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tx_id: Arc::new(AtomicUsize::new(TX - 1)),
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};
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device.reset();
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device.init();
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device
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}
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fn reset(&mut self) {
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// Disable interrupts
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self.write(REG_IMC, 0xFFFF);
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// Reset device
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let ctrl = self.read(REG_CTRL);
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self.write(REG_CTRL, ctrl | CTRL_RST); // Reset
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sys::time::nanowait(500); // TODO: How long should we wait?
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// Disable interrupts again
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self.write(REG_IMC, 0xFFFF);
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// Reset link
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let ctrl = self.read(REG_CTRL) & !CTRL_LRST;
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self.write(REG_CTRL, ctrl);
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}
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fn init(&mut self) {
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self.detect_eeprom();
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self.config.update_mac(self.read_mac());
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self.init_rx();
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self.init_tx();
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self.link_up();
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// TODO: Enable interrupts
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//self.write(REG_IMS, ICR_LSC | ICR_RXDMT0 | ICR_RXT0);
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self.write(REG_IMS, 0);
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// Clear interrupts
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self.read(REG_ICR);
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}
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fn init_rx(&mut self) {
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// Multicast Table Array
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for i in 0..128 {
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self.write(REG_MTA + i * 4, 0);
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}
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// Descriptors
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let mut rx_descs = self.rx_descs.lock();
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let n = RX_BUFFERS_COUNT;
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for i in 0..n {
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rx_descs[i].addr = self.rx_buffers[i].addr();
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rx_descs[i].status = 0;
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}
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let ptr = ptr::addr_of!(rx_descs[0]) as *const u8;
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let phys_addr = sys::allocator::phys_addr(ptr);
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// Ring address and length
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self.write(REG_RDBAL, phys_addr.get_bits(0..32) as u32);
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self.write(REG_RDBAH, phys_addr.get_bits(32..64) as u32);
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self.write(REG_RDLEN, (n * 16) as u32);
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// Ring head and tail
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self.write(REG_RDH, 0);
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self.write(REG_RDT, (n - 1) as u32);
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// Control Register
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self.write(REG_RCTL, RCTL_EN | RCTL_BAM | RCTL_SECRC | RCTL_BSIZE);
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}
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fn init_tx(&mut self) {
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// Descriptors
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let mut tx_descs = self.tx_descs.lock();
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let n = TX_BUFFERS_COUNT;
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for i in 0..n {
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tx_descs[i].addr = self.tx_buffers[i].addr();
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tx_descs[i].cmd = 0;
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tx_descs[i].status = TSTA_DD as u8;
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}
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let ptr = ptr::addr_of!(tx_descs[0]) as *const _;
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let phys_addr = sys::allocator::phys_addr(ptr);
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// Ring address and length
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self.write(REG_TDBAL, phys_addr.get_bits(0..32) as u32);
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self.write(REG_TDBAH, phys_addr.get_bits(32..64) as u32);
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self.write(REG_TDLEN, (n as u32) * 16);
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// Ring head and tail
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self.write(REG_TDH, 0);
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self.write(REG_TDT, 0);
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// Control Register
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// NOTE: MULR is only needed for Intel I217-LM
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self.write(REG_TCTL, TCTL_EN // Transmit Enable
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| TCTL_PSP // Pad Short Packets
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| (0x0F << TCTL_CT_SHIFT) // Collision Threshold
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| (0x3F << TCTL_COLD_SHIFT) // Collision Distance
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| TCTL_MULR); // Multiple Request Support
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// Inter Packet Gap (3 x 10 bits)
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self.write(REG_TIPG, TIPG_IPGT // IPG Transmit Time
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| (TIPG_IPGR1 << 10) // IPG Receive Time 1
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| (TIPG_IPGR2 << 20)); // IPG Receive Time 2
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}
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fn read_mac(&self) -> EthernetAddress {
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let mut mac = [0; 6];
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if self.has_eeprom {
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let mut tmp;
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tmp = self.read_eeprom(0);
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mac[0] = (tmp &0xff) as u8;
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mac[1] = (tmp >> 8) as u8;
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tmp = self.read_eeprom(1);
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mac[2] = (tmp &0xff) as u8;
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mac[3] = (tmp >> 8) as u8;
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tmp = self.read_eeprom(2);
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mac[4] = (tmp &0xff) as u8;
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mac[5] = (tmp >> 8) as u8;
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} else {
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unsafe {
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let phys = self.mem_base + 0x5400;
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let addr = sys::mem::phys_to_virt(phys).as_u64();
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let mac_32 = core::ptr::read_volatile(addr as *const u32);
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if mac_32 != 0 {
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let mac_8 = slice::from_raw_parts(addr as *const u8, 6);
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mac[..].clone_from_slice(mac_8);
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}
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}
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}
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EthernetAddress::from_bytes(&mac[..])
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}
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fn link_up(&self) {
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let ctrl = self.read(REG_CTRL);
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self.write(REG_CTRL, ctrl | CTRL_SLU | CTRL_ASDE & !CTRL_LRST);
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}
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fn write(&self, addr: u16, data: u32) {
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unsafe {
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if self.bar_type == 0 {
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let phys = self.mem_base + addr as u64;
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let addr = sys::mem::phys_to_virt(phys).as_u64() as *mut u32;
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core::ptr::write_volatile(addr, data);
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} else {
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Port::new(self.io_base + IO_ADDR).write(addr);
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Port::new(self.io_base + IO_DATA).write(data);
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}
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}
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}
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fn read(&self, addr: u16) -> u32 {
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unsafe {
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if self.bar_type == 0 {
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let phys = self.mem_base + addr as u64;
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let addr = sys::mem::phys_to_virt(phys).as_u64() as *mut u32;
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core::ptr::read_volatile(addr)
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} else {
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Port::new(self.io_base + IO_ADDR).write(addr);
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Port::new(self.io_base + IO_DATA).read()
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}
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}
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}
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fn detect_eeprom(&mut self) {
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self.write(REG_EECD, 1);
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let mut i = 0;
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while !self.has_eeprom && i < 1000 {
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self.has_eeprom = self.read(REG_EECD) & 0x10 > 0;
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i += 1;
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}
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}
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fn read_eeprom(&self, addr: u16) -> u32 {
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let e = if self.has_eeprom { 4 } else { 0 };
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self.write(REG_EECD, 1 | ((addr as u32) << 2 * e));
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let mut res = 0;
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while res & (1 << 1 * e) == 0 {
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res = self.read(REG_EECD);
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}
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(res >> 16) & 0xFFFF
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}
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#[allow(dead_code)]
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fn debug(&self) {
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// Registers
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debug!("NET E1000: ICR: {:#034b}", self.read(REG_ICR));
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debug!("NET E1000: CTRL: {:#034b}", self.read(REG_CTRL));
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debug!("NET E1000: STATUS: {:#034b}", self.read(REG_STATUS));
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debug!("NET E1000: RDH -> {}", self.read(REG_RDH));
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debug!("NET E1000: RDT -> {}", self.read(REG_RDT));
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debug!("NET E1000: TDH -> {}", self.read(REG_TDH));
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debug!("NET E1000: TDT -> {}", self.read(REG_TDT));
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// Receive descriptors
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let rx_descs = self.rx_descs.lock();
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for i in 0..RX_BUFFERS_COUNT {
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let ptr = ptr::addr_of!(rx_descs[i]) as *const u8;
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let phy = sys::allocator::phys_addr(ptr);
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debug!(
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"NET E1000: [{}] {:?} ({:#X} -> {:#X})",
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i, rx_descs[i], ptr as u64, phy
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);
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}
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// Transmit descriptors
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let tx_descs = self.tx_descs.lock();
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for i in 0..TX_BUFFERS_COUNT {
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let ptr = ptr::addr_of!(tx_descs[i]) as *const u8;
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let phy = sys::allocator::phys_addr(ptr);
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debug!(
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"NET E1000: [{}] {:?} ({:#X} -> {:#X})",
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i, tx_descs[i], ptr as u64, phy
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);
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}
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}
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}
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impl EthernetDeviceIO for Device {
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fn config(&self) -> Arc<Config> {
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self.config.clone()
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}
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fn stats(&self) -> Arc<Stats> {
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self.stats.clone()
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}
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fn receive_packet(&mut self) -> Option<Vec<u8>> {
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let icr = self.read(REG_ICR);
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self.write(REG_ICR, icr);
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// Link Status Change
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if icr & ICR_LSC > 0 {
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if self.read(REG_STATUS) & DSTA_LU == 0 {
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self.link_up();
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return None;
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}
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}
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// Receive Descriptor Minimum Threshold
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if icr & ICR_RXDMT0 > 0 {
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// TODO
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}
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// Receiver Timer Interrupt
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if icr & ICR_RXT0 > 0 {
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// TODO
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}
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let rx_id = self.rx_id.load(Ordering::SeqCst);
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let mut rx_descs = self.rx_descs.lock();
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// If hardware is done with the current descriptor
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if rx_descs[rx_id].status & RSTA_DD > 0 {
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if rx_descs[rx_id].status & RSTA_EOP == 0 {
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// FIXME: this is not the last descriptor for the packet
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}
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self.rx_id.store((rx_id + 1) % RX_BUFFERS_COUNT, Ordering::SeqCst);
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let n = rx_descs[rx_id].len as usize;
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let buf = self.rx_buffers[rx_id][0..n].to_vec();
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rx_descs[rx_id].status = 0; // Driver is done
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self.write(REG_RDT, rx_id as u32);
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return Some(buf);
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}
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None
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}
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fn transmit_packet(&mut self, len: usize) {
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let tx_id = self.tx_id.load(Ordering::SeqCst);
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let mut tx_descs = self.tx_descs.lock();
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debug_assert_eq!(tx_descs[tx_id].addr, self.tx_buffers[tx_id].addr());
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// Setup descriptor
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tx_descs[tx_id].len = len as u16;
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tx_descs[tx_id].cmd = CMD_EOP | CMD_IFCS | CMD_RS;
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tx_descs[tx_id].status = 0; // Driver is done
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// Let the hardware handle the descriptor
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self.write(REG_TDT, ((tx_id + 1) % TX_BUFFERS_COUNT) as u32);
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}
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fn next_tx_buffer(&mut self, len: usize) -> &mut [u8] {
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let tx_id = (self.tx_id.load(Ordering::SeqCst) + 1) % TX_BUFFERS_COUNT;
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self.tx_id.store(tx_id, Ordering::SeqCst);
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&mut self.tx_buffers[tx_id][0..len]
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}
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}
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#[test_case]
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fn test_driver() {
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assert_eq!(core::mem::size_of::<RxDesc>(), 16);
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assert_eq!(core::mem::size_of::<TxDesc>(), 16);
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}
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