Add NOT
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index.html
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index.html
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<div id="content" class="content">
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<div id="content" class="content">
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<h1 class="title">ocpu</h1>
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<h1 class="title">ocpu</h1>
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<div id="outline-container-orgfb92850" class="outline-2">
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<div id="outline-container-org59ce0e8" class="outline-2">
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<h2 id="orgfb92850">GRU ocpu - yet another cpu design</h2>
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<h2 id="org59ce0e8">GRU ocpu - yet another cpu design</h2>
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<div class="outline-text-2" id="text-orgfb92850">
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<div class="outline-text-2" id="text-org59ce0e8">
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</div>
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</div>
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<div id="outline-container-org3484607" class="outline-3">
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<div id="outline-container-orgf798eeb" class="outline-3">
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<h3 id="org3484607">Features</h3>
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<h3 id="orgf798eeb">Features</h3>
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<div class="outline-text-3" id="text-org3484607">
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<div class="outline-text-3" id="text-orgf798eeb">
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<ul class="org-ul">
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<ul class="org-ul">
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<li>little endian</li>
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<li>little endian</li>
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<li>16-bit</li>
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<li>16-bit</li>
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</ul>
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</ul>
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</div>
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</div>
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</div>
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</div>
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<div id="outline-container-orge29449e" class="outline-3">
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<div id="outline-container-orgc029f05" class="outline-3">
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<h3 id="orge29449e">Registers</h3>
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<h3 id="orgc029f05">Registers</h3>
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<div class="outline-text-3" id="text-orge29449e">
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<div class="outline-text-3" id="text-orgc029f05">
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<table border="2" cellspacing="0" cellpadding="6" rules="groups" frame="hsides">
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<table border="2" cellspacing="0" cellpadding="6" rules="groups" frame="hsides">
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</div>
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</div>
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</div>
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</div>
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<div id="outline-container-orga7d5604" class="outline-3">
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<div id="outline-container-orged9566e" class="outline-3">
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<h3 id="orga7d5604">Instuctions</h3>
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<h3 id="orged9566e">Instuctions</h3>
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<div class="outline-text-3" id="text-orga7d5604">
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<div class="outline-text-3" id="text-orged9566e">
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<table border="2" cellspacing="0" cellpadding="6" rules="groups" frame="hsides">
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<table border="2" cellspacing="0" cellpadding="6" rules="groups" frame="hsides">
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</tbody>
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</tbody>
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<tbody>
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<tbody>
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<tr>
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<tr>
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<td class="org-left">AND reg, imm16</td>
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<td class="org-left">NOT reg</td>
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<td class="org-right">0x20</td>
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<td class="org-right">0x20</td>
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<td class="org-left">Logical NOT</td>
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</tr>
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</tbody>
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<tbody>
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<tr>
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<td class="org-left">AND reg, imm16</td>
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<td class="org-right">0x21</td>
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<td class="org-left">Logical AND</td>
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<td class="org-left">Logical AND</td>
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</tr>
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</tr>
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<tr>
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<tr>
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<td class="org-left">AND reg, reg</td>
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<td class="org-left">AND reg, reg</td>
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<td class="org-right">0xC0</td>
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<td class="org-left"> </td>
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</tr>
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</tbody>
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<tbody>
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<tr>
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<td class="org-left">OR reg, imm16</td>
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<td class="org-right">0x21</td>
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<td class="org-left">Logical OR</td>
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</tr>
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<tr>
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<td class="org-left">OR reg, reg</td>
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<td class="org-right">0xC1</td>
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<td class="org-right">0xC1</td>
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<td class="org-left"> </td>
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<td class="org-left"> </td>
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</tr>
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</tr>
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</tbody>
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</tbody>
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<tbody>
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<tbody>
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<tr>
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<tr>
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<td class="org-left">NOR reg, imm16</td>
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<td class="org-left">OR reg, imm16</td>
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<td class="org-right">0x22</td>
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<td class="org-right">0x22</td>
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<td class="org-left">Logical NOR</td>
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<td class="org-left">Logical OR</td>
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</tr>
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</tr>
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<tr>
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<tr>
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<td class="org-left">NOR reg, reg</td>
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<td class="org-left">OR reg, reg</td>
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<td class="org-right">0xC2</td>
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<td class="org-right">0xC2</td>
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<td class="org-left"> </td>
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<td class="org-left"> </td>
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</tr>
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</tr>
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</tbody>
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</tbody>
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<tbody>
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<tbody>
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<tr>
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<tr>
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<td class="org-left">XOR reg, imm16</td>
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<td class="org-left">NOR reg, imm16</td>
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<td class="org-right">0x23</td>
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<td class="org-right">0x23</td>
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<td class="org-left">Logical XOR</td>
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<td class="org-left">Logical NOR</td>
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</tr>
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</tr>
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<tr>
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<tr>
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<td class="org-left">XOR reg, reg</td>
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<td class="org-left">NOR reg, reg</td>
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<td class="org-right">0xC3</td>
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<td class="org-right">0xC3</td>
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<td class="org-left"> </td>
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<td class="org-left"> </td>
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</tr>
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</tr>
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</tbody>
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</tbody>
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<tbody>
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<tbody>
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<tr>
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<tr>
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<td class="org-left">NAND reg, imm16</td>
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<td class="org-left">XOR reg, imm16</td>
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<td class="org-right">0x24</td>
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<td class="org-right">0x24</td>
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<td class="org-left">Logical NAND</td>
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<td class="org-left">Logical XOR</td>
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</tr>
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</tr>
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<tr>
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<tr>
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<td class="org-left">NAND reg, reg</td>
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<td class="org-left">XOR reg, reg</td>
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<td class="org-right">0xC4</td>
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<td class="org-right">0xC4</td>
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<td class="org-left"> </td>
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<td class="org-left"> </td>
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</tr>
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</tr>
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</tbody>
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</tbody>
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<tbody>
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<tbody>
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<tr>
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<tr>
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<td class="org-left">CMP reg, imm16, imm16</td>
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<td class="org-left">NAND reg, imm16</td>
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<td class="org-right">0x25</td>
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<td class="org-right">0x25</td>
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<td class="org-left">Logical NAND</td>
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</tr>
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<tr>
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<td class="org-left">NAND reg, reg</td>
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<td class="org-right">0xC5</td>
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<td class="org-left"> </td>
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</tr>
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</tbody>
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<tbody>
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<tr>
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<td class="org-left">CMP reg, imm16, imm16</td>
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<td class="org-right">0x26</td>
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<td class="org-left">Compare</td>
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<td class="org-left">Compare</td>
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</tr>
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</tr>
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<tr>
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<tr>
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<td class="org-left">CMP reg, reg, imm16</td>
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<td class="org-left">CMP reg, reg, imm16</td>
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<td class="org-right">0xC5</td>
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<td class="org-right">0xC6</td>
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<td class="org-left"> </td>
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<td class="org-left"> </td>
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</tr>
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</tr>
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26
ocpu.org
26
ocpu.org
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@ -92,23 +92,25 @@
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|-----------------------+--------+-------------------------------------------|
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|-----------------------+--------+-------------------------------------------|
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| DEC reg | 0x16 | Decrement |
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| DEC reg | 0x16 | Decrement |
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|-----------------------+--------+-------------------------------------------|
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|-----------------------+--------+-------------------------------------------|
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| AND reg, imm16 | 0x20 | Logical AND |
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| NOT reg | 0x20 | Logical NOT |
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| AND reg, reg | 0xC0 | |
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|-----------------------+--------+-------------------------------------------|
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|-----------------------+--------+-------------------------------------------|
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| OR reg, imm16 | 0x21 | Logical OR |
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| AND reg, imm16 | 0x21 | Logical AND |
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| OR reg, reg | 0xC1 | |
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| AND reg, reg | 0xC1 | |
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|-----------------------+--------+-------------------------------------------|
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|-----------------------+--------+-------------------------------------------|
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| NOR reg, imm16 | 0x22 | Logical NOR |
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| OR reg, imm16 | 0x22 | Logical OR |
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| NOR reg, reg | 0xC2 | |
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| OR reg, reg | 0xC2 | |
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|-----------------------+--------+-------------------------------------------|
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|-----------------------+--------+-------------------------------------------|
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| XOR reg, imm16 | 0x23 | Logical XOR |
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| NOR reg, imm16 | 0x23 | Logical NOR |
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| XOR reg, reg | 0xC3 | |
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| NOR reg, reg | 0xC3 | |
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|-----------------------+--------+-------------------------------------------|
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|-----------------------+--------+-------------------------------------------|
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| NAND reg, imm16 | 0x24 | Logical NAND |
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| XOR reg, imm16 | 0x24 | Logical XOR |
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| NAND reg, reg | 0xC4 | |
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| XOR reg, reg | 0xC4 | |
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|-----------------------+--------+-------------------------------------------|
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|-----------------------+--------+-------------------------------------------|
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| CMP reg, imm16, imm16 | 0x25 | Compare |
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| NAND reg, imm16 | 0x25 | Logical NAND |
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| CMP reg, reg, imm16 | 0xC5 | |
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| NAND reg, reg | 0xC5 | |
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|-----------------------+--------+-------------------------------------------|
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| CMP reg, imm16, imm16 | 0x26 | Compare |
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| CMP reg, reg, imm16 | 0xC6 | |
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| CMP reg, reg, reg | | |
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| CMP reg, reg, reg | | |
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|-----------------------+--------+-------------------------------------------|
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|-----------------------+--------+-------------------------------------------|
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| PUSH imm16 | 0x30 | Push to stack |
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| PUSH imm16 | 0x30 | Push to stack |
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