Added all sources.
This commit is contained in:
Lucian
parent
5a01162013
commit
367d4475cf
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version:1
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eof:
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<?xml version="1.0" encoding="UTF-8" ?>
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<document>
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<!--The data in this file is primarily intended for consumption by Xilinx tools.
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The structure and the elements are likely to change over the next few releases.
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This means code written to parse this file will need to be revisited each subsequent release.-->
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<application name="pa" timeStamp="Sat Nov 21 18:48:32 2020">
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</item>
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<property name="MainMenuMgr_TOOLS" value="4" type="GuiHandlerData"/>
|
||||
<property name="MsgTreePanel_MESSAGE_VIEW_TREE" value="15" type="GuiHandlerData"/>
|
||||
<property name="MsgView_ERROR_MESSAGES" value="1" type="GuiHandlerData"/>
|
||||
<property name="PACodeEditor_FIND_IN_FILES" value="1" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_ADD_SOURCES" value="12" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_AUTO_UPDATE_HIER" value="15" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_SET_AS_TOP" value="1" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_SIMULATION_CLOSE" value="5" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_SIMULATION_RUN_BEHAVIORAL" value="67" type="GuiHandlerData"/>
|
||||
<property name="PAViews_CODE" value="51" type="GuiHandlerData"/>
|
||||
<property name="PAViews_PROJECT_SUMMARY" value="38" type="GuiHandlerData"/>
|
||||
<property name="ProgressDialog_BACKGROUND" value="2" type="GuiHandlerData"/>
|
||||
<property name="ProgressDialog_CANCEL" value="1" type="GuiHandlerData"/>
|
||||
<property name="ProjectNameChooser_PROJECT_NAME" value="1" type="GuiHandlerData"/>
|
||||
<property name="ProjectSettingsSimulationPanel_ENABLE_INCREMENTAL_COMPILATION" value="1" type="GuiHandlerData"/>
|
||||
<property name="ProjectSettingsSimulationPanel_TABBED_PANE" value="3" type="GuiHandlerData"/>
|
||||
<property name="RDICommands_DELETE" value="1" type="GuiHandlerData"/>
|
||||
<property name="RDICommands_SAVE_FILE_AS" value="1" type="GuiHandlerData"/>
|
||||
<property name="RDIViews_WAVEFORM_VIEWER" value="54" type="GuiHandlerData"/>
|
||||
<property name="SaveProjectUtils_CANCEL" value="1" type="GuiHandlerData"/>
|
||||
<property name="SaveProjectUtils_SAVE" value="15" type="GuiHandlerData"/>
|
||||
<property name="SearchCommandComponent_QUICK_ACCESS" value="6" type="GuiHandlerData"/>
|
||||
<property name="SelectTopModuleDialog_SELECT_TOP_MODULE" value="1" type="GuiHandlerData"/>
|
||||
<property name="SettingsDialog_OPTIONS_TREE" value="7" type="GuiHandlerData"/>
|
||||
<property name="SettingsDialog_PROJECT_TREE" value="1" type="GuiHandlerData"/>
|
||||
<property name="SettingsEditorPage_CUSTOM_EDITOR" value="2" type="GuiHandlerData"/>
|
||||
<property name="SettingsEditorPage_ENTER_COMMAND_LINE_FOR_CUSTOM" value="2" type="GuiHandlerData"/>
|
||||
<property name="SettingsEditorPage_USE_THIS_DROP_DOWN_LIST_BOX_TO_SELECT" value="5" type="GuiHandlerData"/>
|
||||
<property name="SimulationObjectsPanel_SIMULATION_OBJECTS_TREE_TABLE" value="95" type="GuiHandlerData"/>
|
||||
<property name="SimulationScopesPanel_SIMULATE_SCOPE_TABLE" value="195" type="GuiHandlerData"/>
|
||||
<property name="SrcChooserPanel_ADD_HDL_AND_NETLIST_FILES_TO_YOUR_PROJECT" value="4" type="GuiHandlerData"/>
|
||||
<property name="SrcChooserPanel_ADD_OR_CREATE_SOURCE_FILE" value="2" type="GuiHandlerData"/>
|
||||
<property name="SrcChooserPanel_CREATE_FILE" value="11" type="GuiHandlerData"/>
|
||||
<property name="SrcMenu_IP_HIERARCHY" value="17" type="GuiHandlerData"/>
|
||||
<property name="SyntheticaGettingStartedView_RECENT_PROJECTS" value="14" type="GuiHandlerData"/>
|
||||
<property name="WaveformNameTree_WAVEFORM_NAME_TREE" value="17" type="GuiHandlerData"/>
|
||||
</item>
|
||||
<item name="Other">
|
||||
<property name="GuiMode" value="25" type="GuiMode"/>
|
||||
<property name="BatchMode" value="0" type="BatchMode"/>
|
||||
<property name="TclMode" value="19" type="TclMode"/>
|
||||
</item>
|
||||
</section>
|
||||
</application>
|
||||
</document>
|
||||
|
|
@ -1,4 +0,0 @@
|
|||
version:1
|
||||
7873696d:7873696d5c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73696d5f6d6f6465:64656661756c743a3a6265686176696f72616c:00:00
|
||||
7873696d:7873696d5c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73696d5f74797065:64656661756c743a3a:00:00
|
||||
eof:241934075
|
||||
|
|
@ -1,6 +0,0 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!-- Product Version: Vivado v2018.3 (64-bit) -->
|
||||
<!-- -->
|
||||
<!-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. -->
|
||||
|
||||
<labtools version="1" minor="0"/>
|
||||
|
|
@ -1 +0,0 @@
|
|||
The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended.
|
||||
|
|
@ -1,18 +0,0 @@
|
|||
00008133 00108093 0020F1B3 0010E213 0042A223 00802603 04090E63
|
||||
|
||||
add x2, x1, x0 - 0000000 00000 00001 000 00010 0110011 - 00008133
|
||||
|
||||
addi x1, x1, 1 - 000000000001 00001 000 00001 0010011 - 00108093
|
||||
|
||||
and x3, x1, x2 - 0000000 00010 00001 111 00011 0110011 - 0020F1B3
|
||||
|
||||
ori x4, x1, 1 - 000000000001 00001 110 00100 0010011 - 0010E213
|
||||
|
||||
sw x4, 4(x5) - 0000000 00100 00101 010 00100 0100011 - 0042A223
|
||||
|
||||
lw x12, 8(x0) - 000000001000 00000 010 01100 0000011 - 00802603
|
||||
|
||||
beq x18, x0, 5c - 0 0000010 00000 10010 000 1110 0 1100011 - 04090E63
|
||||
|
||||
5c = 0 0000 0101 1100
|
||||
18 = 16 + 2 = 10010
|
||||
|
|
@ -1,11 +0,0 @@
|
|||
set curr_wave [current_wave_config]
|
||||
if { [string length $curr_wave] == 0 } {
|
||||
if { [llength [get_objects]] > 0} {
|
||||
add_wave /
|
||||
set_property needs_save false [current_wave_config]
|
||||
} else {
|
||||
send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
|
||||
}
|
||||
}
|
||||
|
||||
run 1000ns
|
||||
Binary file not shown.
|
|
@ -1,19 +0,0 @@
|
|||
# compile verilog/system verilog design source files
|
||||
verilog xil_defaultlib \
|
||||
"../../../../RISC_V.srcs/sources_1/new/ID.v" \
|
||||
"../../../../RISC_V.srcs/sources_1/new/IF.v" \
|
||||
"../../../../RISC_V.srcs/sources_1/new/IF_ID_REG.v" \
|
||||
"../../../../RISC_V.srcs/sources_1/new/PC.v" \
|
||||
"../../../../RISC_V.srcs/sources_1/new/RISC_V_IF_ID.v" \
|
||||
"../../../../RISC_V.srcs/sources_1/new/adder.v" \
|
||||
"../../../../RISC_V.srcs/sources_1/new/imm_gen.v" \
|
||||
"../../../../RISC_V.srcs/sources_1/new/instruction_memory.v" \
|
||||
"../../../../RISC_V.srcs/sources_1/new/mux2_1.v" \
|
||||
"../../../../RISC_V.srcs/sources_1/new/registers.v" \
|
||||
"../../../../RISC_V.srcs/sources_1/new/RISC_V_IF_ID_TB.v" \
|
||||
|
||||
# compile glbl module
|
||||
verilog xil_defaultlib "glbl.v"
|
||||
|
||||
# Do not sort compile order
|
||||
nosort
|
||||
|
|
@ -1,18 +0,0 @@
|
|||
00008133 00108093 0020F1B3 0010E213 0042A223 00802603 04090E63
|
||||
|
||||
add x2, x1, x0 - 0000000 00000 00001 000 00010 0110011 - 00008133
|
||||
|
||||
addi x1, x1, 1 - 000000000001 00001 000 00001 0010011 - 00108093
|
||||
|
||||
and x3, x1, x2 - 0000000 00010 00001 111 00011 0110011 - 0020F1B3
|
||||
|
||||
ori x4, x1, 1 - 000000000001 00001 110 00100 0010011 - 0010E213
|
||||
|
||||
sw x4, 4(x5) - 0000000 00100 00101 010 00100 0100011 - 0042A223
|
||||
|
||||
lw x12, 8(x0) - 000000001000 00000 010 01100 0000011 - 00802603
|
||||
|
||||
beq x18, x0, 5c - 0 0000010 00000 10010 000 1110 0 1100011 - 04090E63
|
||||
|
||||
5c = 0 0000 0101 1100
|
||||
18 = 16 + 2 = 10010
|
||||
|
|
@ -1,25 +0,0 @@
|
|||
@echo off
|
||||
REM ****************************************************************************
|
||||
REM Vivado (TM) v2018.3 (64-bit)
|
||||
REM
|
||||
REM Filename : compile.bat
|
||||
REM Simulator : Xilinx Vivado Simulator
|
||||
REM Description : Script for compiling the simulation design source files
|
||||
REM
|
||||
REM Generated by Vivado on Sat Nov 21 18:32:22 +0200 2020
|
||||
REM SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
|
||||
REM
|
||||
REM Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
|
||||
REM
|
||||
REM usage: compile.bat
|
||||
REM
|
||||
REM ****************************************************************************
|
||||
echo "xvlog --relax -prj RISC_V_IF_ID_TB_vlog.prj"
|
||||
call xvlog --relax -prj RISC_V_IF_ID_TB_vlog.prj -log xvlog.log
|
||||
call type xvlog.log > compile.log
|
||||
if "%errorlevel%"=="1" goto END
|
||||
if "%errorlevel%"=="0" goto SUCCESS
|
||||
:END
|
||||
exit 1
|
||||
:SUCCESS
|
||||
exit 0
|
||||
|
|
@ -1,25 +0,0 @@
|
|||
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/VivadoProjects/RISC_V/RISC_V.srcs/sources_1/new/ID.v" into library xil_defaultlib
|
||||
INFO: [VRFC 10-311] analyzing module ID
|
||||
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/VivadoProjects/RISC_V/RISC_V.srcs/sources_1/new/IF.v" into library xil_defaultlib
|
||||
INFO: [VRFC 10-311] analyzing module IF
|
||||
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/VivadoProjects/RISC_V/RISC_V.srcs/sources_1/new/IF_ID_REG.v" into library xil_defaultlib
|
||||
INFO: [VRFC 10-311] analyzing module IF_ID_REG
|
||||
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/VivadoProjects/RISC_V/RISC_V.srcs/sources_1/new/PC.v" into library xil_defaultlib
|
||||
INFO: [VRFC 10-311] analyzing module PC
|
||||
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/VivadoProjects/RISC_V/RISC_V.srcs/sources_1/new/RISC_V_IF_ID.v" into library xil_defaultlib
|
||||
INFO: [VRFC 10-311] analyzing module RISC_V_IF_ID
|
||||
WARNING: [VRFC 10-3676] redeclaration of ansi port 'PC_ID' is not allowed [D:/VivadoProjects/RISC_V/RISC_V.srcs/sources_1/new/RISC_V_IF_ID.v:44]
|
||||
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/VivadoProjects/RISC_V/RISC_V.srcs/sources_1/new/adder.v" into library xil_defaultlib
|
||||
INFO: [VRFC 10-311] analyzing module adder
|
||||
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/VivadoProjects/RISC_V/RISC_V.srcs/sources_1/new/imm_gen.v" into library xil_defaultlib
|
||||
INFO: [VRFC 10-311] analyzing module imm_gen
|
||||
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/VivadoProjects/RISC_V/RISC_V.srcs/sources_1/new/instruction_memory.v" into library xil_defaultlib
|
||||
INFO: [VRFC 10-311] analyzing module instruction_memory
|
||||
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/VivadoProjects/RISC_V/RISC_V.srcs/sources_1/new/mux2_1.v" into library xil_defaultlib
|
||||
INFO: [VRFC 10-311] analyzing module mux2_1
|
||||
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/VivadoProjects/RISC_V/RISC_V.srcs/sources_1/new/registers.v" into library xil_defaultlib
|
||||
INFO: [VRFC 10-311] analyzing module registers
|
||||
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/VivadoProjects/RISC_V/RISC_V.srcs/sources_1/new/RISC_V_IF_ID_TB.v" into library xil_defaultlib
|
||||
INFO: [VRFC 10-311] analyzing module RISC_V_IF_ID_TB
|
||||
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/VivadoProjects/RISC_V/RISC_V.sim/sim_1/behav/xsim/glbl.v" into library xil_defaultlib
|
||||
INFO: [VRFC 10-311] analyzing module glbl
|
||||
|
|
@ -1,23 +0,0 @@
|
|||
@echo off
|
||||
REM ****************************************************************************
|
||||
REM Vivado (TM) v2018.3 (64-bit)
|
||||
REM
|
||||
REM Filename : elaborate.bat
|
||||
REM Simulator : Xilinx Vivado Simulator
|
||||
REM Description : Script for elaborating the compiled design
|
||||
REM
|
||||
REM Generated by Vivado on Sat Nov 21 18:32:30 +0200 2020
|
||||
REM SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
|
||||
REM
|
||||
REM Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
|
||||
REM
|
||||
REM usage: elaborate.bat
|
||||
REM
|
||||
REM ****************************************************************************
|
||||
call xelab -wto ee467e506e3e426b91b11db7a6f036e4 --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot RISC_V_IF_ID_TB_behav xil_defaultlib.RISC_V_IF_ID_TB xil_defaultlib.glbl -log elaborate.log
|
||||
if "%errorlevel%"=="0" goto SUCCESS
|
||||
if "%errorlevel%"=="1" goto END
|
||||
:END
|
||||
exit 1
|
||||
:SUCCESS
|
||||
exit 0
|
||||
|
|
@ -1,22 +0,0 @@
|
|||
Vivado Simulator 2018.3
|
||||
Copyright 1986-1999, 2001-2018 Xilinx, Inc. All Rights Reserved.
|
||||
Running: D:/Vivado/2018.3/bin/unwrapped/win64.o/xelab.exe -wto ee467e506e3e426b91b11db7a6f036e4 --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot RISC_V_IF_ID_TB_behav xil_defaultlib.RISC_V_IF_ID_TB xil_defaultlib.glbl -log elaborate.log
|
||||
Using 2 slave threads.
|
||||
Starting static elaboration
|
||||
Completed static elaboration
|
||||
Starting simulation data flow analysis
|
||||
Completed simulation data flow analysis
|
||||
Time Resolution for simulation is 1ps
|
||||
Compiling module xil_defaultlib.PC
|
||||
Compiling module xil_defaultlib.instruction_memory
|
||||
Compiling module xil_defaultlib.adder
|
||||
Compiling module xil_defaultlib.mux2_1
|
||||
Compiling module xil_defaultlib.IF
|
||||
Compiling module xil_defaultlib.IF_ID_REG
|
||||
Compiling module xil_defaultlib.registers
|
||||
Compiling module xil_defaultlib.imm_gen
|
||||
Compiling module xil_defaultlib.ID
|
||||
Compiling module xil_defaultlib.RISC_V_IF_ID
|
||||
Compiling module xil_defaultlib.RISC_V_IF_ID_TB
|
||||
Compiling module xil_defaultlib.glbl
|
||||
Built simulation snapshot RISC_V_IF_ID_TB_behav
|
||||
|
|
@ -1,71 +0,0 @@
|
|||
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
|
||||
`ifndef GLBL
|
||||
`define GLBL
|
||||
`timescale 1 ps / 1 ps
|
||||
|
||||
module glbl ();
|
||||
|
||||
parameter ROC_WIDTH = 100000;
|
||||
parameter TOC_WIDTH = 0;
|
||||
|
||||
//-------- STARTUP Globals --------------
|
||||
wire GSR;
|
||||
wire GTS;
|
||||
wire GWE;
|
||||
wire PRLD;
|
||||
tri1 p_up_tmp;
|
||||
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
|
||||
|
||||
wire PROGB_GLBL;
|
||||
wire CCLKO_GLBL;
|
||||
wire FCSBO_GLBL;
|
||||
wire [3:0] DO_GLBL;
|
||||
wire [3:0] DI_GLBL;
|
||||
|
||||
reg GSR_int;
|
||||
reg GTS_int;
|
||||
reg PRLD_int;
|
||||
|
||||
//-------- JTAG Globals --------------
|
||||
wire JTAG_TDO_GLBL;
|
||||
wire JTAG_TCK_GLBL;
|
||||
wire JTAG_TDI_GLBL;
|
||||
wire JTAG_TMS_GLBL;
|
||||
wire JTAG_TRST_GLBL;
|
||||
|
||||
reg JTAG_CAPTURE_GLBL;
|
||||
reg JTAG_RESET_GLBL;
|
||||
reg JTAG_SHIFT_GLBL;
|
||||
reg JTAG_UPDATE_GLBL;
|
||||
reg JTAG_RUNTEST_GLBL;
|
||||
|
||||
reg JTAG_SEL1_GLBL = 0;
|
||||
reg JTAG_SEL2_GLBL = 0 ;
|
||||
reg JTAG_SEL3_GLBL = 0;
|
||||
reg JTAG_SEL4_GLBL = 0;
|
||||
|
||||
reg JTAG_USER_TDO1_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO2_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO3_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO4_GLBL = 1'bz;
|
||||
|
||||
assign (strong1, weak0) GSR = GSR_int;
|
||||
assign (strong1, weak0) GTS = GTS_int;
|
||||
assign (weak1, weak0) PRLD = PRLD_int;
|
||||
|
||||
initial begin
|
||||
GSR_int = 1'b1;
|
||||
PRLD_int = 1'b1;
|
||||
#(ROC_WIDTH)
|
||||
GSR_int = 1'b0;
|
||||
PRLD_int = 1'b0;
|
||||
end
|
||||
|
||||
initial begin
|
||||
GTS_int = 1'b1;
|
||||
#(TOC_WIDTH)
|
||||
GTS_int = 1'b0;
|
||||
end
|
||||
|
||||
endmodule
|
||||
`endif
|
||||
|
|
@ -1,23 +0,0 @@
|
|||
@echo off
|
||||
REM ****************************************************************************
|
||||
REM Vivado (TM) v2018.3 (64-bit)
|
||||
REM
|
||||
REM Filename : simulate.bat
|
||||
REM Simulator : Xilinx Vivado Simulator
|
||||
REM Description : Script for simulating the design by launching the simulator
|
||||
REM
|
||||
REM Generated by Vivado on Sat Nov 21 18:32:47 +0200 2020
|
||||
REM SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
|
||||
REM
|
||||
REM Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
|
||||
REM
|
||||
REM usage: simulate.bat
|
||||
REM
|
||||
REM ****************************************************************************
|
||||
call xsim RISC_V_IF_ID_TB_behav -key {Behavioral:sim_1:Functional:RISC_V_IF_ID_TB} -tclbatch RISC_V_IF_ID_TB.tcl -log simulate.log
|
||||
if "%errorlevel%"=="0" goto SUCCESS
|
||||
if "%errorlevel%"=="1" goto END
|
||||
:END
|
||||
exit 1
|
||||
:SUCCESS
|
||||
exit 0
|
||||
|
|
@ -1,4 +0,0 @@
|
|||
Vivado Simulator 2018.3
|
||||
Time resolution is 1 ps
|
||||
WARNING: Too many words specified in data file code.mem
|
||||
$finish called at time : 210 ns : File "D:/VivadoProjects/RISC_V/RISC_V.srcs/sources_1/new/RISC_V_IF_ID_TB.v" Line 55
|
||||
|
|
@ -1,12 +0,0 @@
|
|||
#-----------------------------------------------------------
|
||||
# Webtalk v2018.3 (64-bit)
|
||||
# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
|
||||
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
|
||||
# Start of session at: Sat Nov 21 18:34:41 2020
|
||||
# Process ID: 16964
|
||||
# Current directory: D:/VivadoProjects/RISC_V/RISC_V.sim/sim_1/behav/xsim
|
||||
# Command line: wbtcv.exe -mode batch -source D:/VivadoProjects/RISC_V/RISC_V.sim/sim_1/behav/xsim/xsim.dir/RISC_V_IF_ID_TB_behav/webtalk/xsim_webtalk.tcl -notrace
|
||||
# Log file: D:/VivadoProjects/RISC_V/RISC_V.sim/sim_1/behav/xsim/webtalk.log
|
||||
# Journal file: D:/VivadoProjects/RISC_V/RISC_V.sim/sim_1/behav/xsim\webtalk.jou
|
||||
#-----------------------------------------------------------
|
||||
source D:/VivadoProjects/RISC_V/RISC_V.sim/sim_1/behav/xsim/xsim.dir/RISC_V_IF_ID_TB_behav/webtalk/xsim_webtalk.tcl -notrace
|
||||
|
|
@ -1,13 +0,0 @@
|
|||
#-----------------------------------------------------------
|
||||
# Webtalk v2018.3 (64-bit)
|
||||
# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
|
||||
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
|
||||
# Start of session at: Sat Nov 21 18:34:41 2020
|
||||
# Process ID: 16964
|
||||
# Current directory: D:/VivadoProjects/RISC_V/RISC_V.sim/sim_1/behav/xsim
|
||||
# Command line: wbtcv.exe -mode batch -source D:/VivadoProjects/RISC_V/RISC_V.sim/sim_1/behav/xsim/xsim.dir/RISC_V_IF_ID_TB_behav/webtalk/xsim_webtalk.tcl -notrace
|
||||
# Log file: D:/VivadoProjects/RISC_V/RISC_V.sim/sim_1/behav/xsim/webtalk.log
|
||||
# Journal file: D:/VivadoProjects/RISC_V/RISC_V.sim/sim_1/behav/xsim\webtalk.jou
|
||||
#-----------------------------------------------------------
|
||||
source D:/VivadoProjects/RISC_V/RISC_V.sim/sim_1/behav/xsim/xsim.dir/RISC_V_IF_ID_TB_behav/webtalk/xsim_webtalk.tcl -notrace
|
||||
INFO: [Common 17-206] Exiting Webtalk at Sat Nov 21 18:34:42 2020...
|
||||
|
|
@ -1,12 +0,0 @@
|
|||
#-----------------------------------------------------------
|
||||
# Webtalk v2018.3 (64-bit)
|
||||
# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
|
||||
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
|
||||
# Start of session at: Sat Nov 21 18:32:45 2020
|
||||
# Process ID: 15032
|
||||
# Current directory: D:/VivadoProjects/RISC_V/RISC_V.sim/sim_1/behav/xsim
|
||||
# Command line: wbtcv.exe -mode batch -source D:/VivadoProjects/RISC_V/RISC_V.sim/sim_1/behav/xsim/xsim.dir/RISC_V_IF_ID_TB_behav/webtalk/xsim_webtalk.tcl -notrace
|
||||
# Log file: D:/VivadoProjects/RISC_V/RISC_V.sim/sim_1/behav/xsim/webtalk.log
|
||||
# Journal file: D:/VivadoProjects/RISC_V/RISC_V.sim/sim_1/behav/xsim\webtalk.jou
|
||||
#-----------------------------------------------------------
|
||||
source D:/VivadoProjects/RISC_V/RISC_V.sim/sim_1/behav/xsim/xsim.dir/RISC_V_IF_ID_TB_behav/webtalk/xsim_webtalk.tcl -notrace
|
||||
|
|
@ -1,13 +0,0 @@
|
|||
#-----------------------------------------------------------
|
||||
# Webtalk v2018.3 (64-bit)
|
||||
# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
|
||||
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
|
||||
# Start of session at: Sat Nov 21 18:32:45 2020
|
||||
# Process ID: 15032
|
||||
# Current directory: D:/VivadoProjects/RISC_V/RISC_V.sim/sim_1/behav/xsim
|
||||
# Command line: wbtcv.exe -mode batch -source D:/VivadoProjects/RISC_V/RISC_V.sim/sim_1/behav/xsim/xsim.dir/RISC_V_IF_ID_TB_behav/webtalk/xsim_webtalk.tcl -notrace
|
||||
# Log file: D:/VivadoProjects/RISC_V/RISC_V.sim/sim_1/behav/xsim/webtalk.log
|
||||
# Journal file: D:/VivadoProjects/RISC_V/RISC_V.sim/sim_1/behav/xsim\webtalk.jou
|
||||
#-----------------------------------------------------------
|
||||
source D:/VivadoProjects/RISC_V/RISC_V.sim/sim_1/behav/xsim/xsim.dir/RISC_V_IF_ID_TB_behav/webtalk/xsim_webtalk.tcl -notrace
|
||||
INFO: [Common 17-206] Exiting Webtalk at Sat Nov 21 18:32:47 2020...
|
||||
Binary file not shown.
|
|
@ -1 +0,0 @@
|
|||
-wto "ee467e506e3e426b91b11db7a6f036e4" --debug "typical" --relax --mt "2" -L "xil_defaultlib" -L "unisims_ver" -L "unimacro_ver" -L "secureip" --snapshot "RISC_V_IF_ID_TB_behav" "xil_defaultlib.RISC_V_IF_ID_TB" "xil_defaultlib.glbl" -log "elaborate.log"
|
||||
|
|
@ -1 +0,0 @@
|
|||
Breakpoint File Version 1.0
|
||||
|
|
@ -1,5 +0,0 @@
|
|||
1605976363
|
||||
1605976480
|
||||
3
|
||||
1
|
||||
ee467e506e3e426b91b11db7a6f036e4
|
||||
|
|
@ -1,53 +0,0 @@
|
|||
<HTML><HEAD><TITLE>Device Usage Statistics Report</TITLE></HEAD>
|
||||
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'><H3>XSIM Usage Report</H3><BR>
|
||||
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
|
||||
<TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='4'><B>software_version_and_target_device</B></TD></TR>
|
||||
<TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>beta</B></TD><TD>FALSE</TD>
|
||||
<TD BGCOLOR='#DBE5F1'><B>build_version</B></TD><TD>2405991</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>date_generated</B></TD><TD>Sat Nov 21 18:34:40 2020</TD>
|
||||
<TD BGCOLOR='#DBE5F1'><B>os_platform</B></TD><TD>WIN64</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>product_version</B></TD><TD>XSIM v2018.3 (64-bit)</TD>
|
||||
<TD BGCOLOR='#DBE5F1'><B>project_id</B></TD><TD>ee467e506e3e426b91b11db7a6f036e4</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>project_iteration</B></TD><TD>2</TD>
|
||||
<TD BGCOLOR='#DBE5F1'><B>random_id</B></TD><TD>601ffe88-8614-41e5-b20b-50cc1ca6fd12</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>registration_id</B></TD><TD>601ffe88-8614-41e5-b20b-50cc1ca6fd12</TD>
|
||||
<TD BGCOLOR='#DBE5F1'><B>route_design</B></TD><TD>FALSE</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>target_device</B></TD><TD>not_applicable</TD>
|
||||
<TD BGCOLOR='#DBE5F1'><B>target_family</B></TD><TD>not_applicable</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>target_package</B></TD><TD>not_applicable</TD>
|
||||
<TD BGCOLOR='#DBE5F1'><B>target_speed</B></TD><TD>not_applicable</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>tool_flow</B></TD><TD>xsim_vivado</TD>
|
||||
</TR> </TABLE><BR>
|
||||
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
|
||||
<TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='4'><B>user_environment</B></TD></TR>
|
||||
<TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>cpu_name</B></TD><TD>Intel(R) Core(TM) i7-7700HQ CPU @ 2.80GHz</TD>
|
||||
<TD BGCOLOR='#DBE5F1'><B>cpu_speed</B></TD><TD>2808 MHz</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>os_name</B></TD><TD>Microsoft Windows 8 or later , 64-bit</TD>
|
||||
<TD BGCOLOR='#DBE5F1'><B>os_release</B></TD><TD>major release (build 9200)</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>system_ram</B></TD><TD>8.000 GB</TD>
|
||||
<TD BGCOLOR='#DBE5F1'><B>total_processors</B></TD><TD>1</TD>
|
||||
</TR> </TABLE><BR>
|
||||
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
|
||||
<TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='4'><B>vivado_usage</B></TD></TR>
|
||||
</TABLE><BR>
|
||||
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
|
||||
<TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>xsim</B></TD></TR>
|
||||
<TR><TD>
|
||||
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
|
||||
<TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>command_line_options</B></TD></TR>
|
||||
<TR ALIGN='LEFT'> <TD>command=xsim</TD>
|
||||
</TR> </TABLE>
|
||||
</TD></TR>
|
||||
<TR><TD>
|
||||
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
|
||||
<TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>usage</B></TD></TR>
|
||||
<TR ALIGN='LEFT'> <TD>iteration=0</TD>
|
||||
<TD>runtime=210 ns</TD>
|
||||
<TD>simulation_memory=6048_KB</TD>
|
||||
<TD>simulation_time=0.03_sec</TD>
|
||||
</TR><TR ALIGN='LEFT'> <TD>trace_waveform=true</TD>
|
||||
</TR> </TABLE>
|
||||
</TD></TR>
|
||||
</TABLE><BR>
|
||||
</BODY>
|
||||
</HTML>
|
||||
|
|
@ -1,44 +0,0 @@
|
|||
<?xml version="1.0" encoding="UTF-8" ?>
|
||||
<webTalkData fileName='usage_statistics_ext_xsim.xml' majorVersion='1' minorVersion='0' timeStamp='Sat Nov 21 18:34:41 2020'>
|
||||
<section name="__ROOT__" level="0" order="1" description="">
|
||||
<section name="software_version_and_target_device" level="1" order="1" description="">
|
||||
<keyValuePair key="beta" value="FALSE" description="" />
|
||||
<keyValuePair key="build_version" value="2405991" description="" />
|
||||
<keyValuePair key="date_generated" value="Sat Nov 21 18:34:40 2020" description="" />
|
||||
<keyValuePair key="os_platform" value="WIN64" description="" />
|
||||
<keyValuePair key="product_version" value="XSIM v2018.3 (64-bit)" description="" />
|
||||
<keyValuePair key="project_id" value="ee467e506e3e426b91b11db7a6f036e4" description="" />
|
||||
<keyValuePair key="project_iteration" value="2" description="" />
|
||||
<keyValuePair key="random_id" value="601ffe88-8614-41e5-b20b-50cc1ca6fd12" description="" />
|
||||
<keyValuePair key="registration_id" value="601ffe88-8614-41e5-b20b-50cc1ca6fd12" description="" />
|
||||
<keyValuePair key="route_design" value="FALSE" description="" />
|
||||
<keyValuePair key="target_device" value="not_applicable" description="" />
|
||||
<keyValuePair key="target_family" value="not_applicable" description="" />
|
||||
<keyValuePair key="target_package" value="not_applicable" description="" />
|
||||
<keyValuePair key="target_speed" value="not_applicable" description="" />
|
||||
<keyValuePair key="tool_flow" value="xsim_vivado" description="" />
|
||||
</section>
|
||||
<section name="user_environment" level="1" order="2" description="">
|
||||
<keyValuePair key="cpu_name" value="Intel(R) Core(TM) i7-7700HQ CPU @ 2.80GHz" description="" />
|
||||
<keyValuePair key="cpu_speed" value="2808 MHz" description="" />
|
||||
<keyValuePair key="os_name" value="Microsoft Windows 8 or later , 64-bit" description="" />
|
||||
<keyValuePair key="os_release" value="major release (build 9200)" description="" />
|
||||
<keyValuePair key="system_ram" value="8.000 GB" description="" />
|
||||
<keyValuePair key="total_processors" value="1" description="" />
|
||||
</section>
|
||||
<section name="vivado_usage" level="1" order="3" description="">
|
||||
</section>
|
||||
<section name="xsim" level="1" order="4" description="">
|
||||
<section name="command_line_options" level="2" order="1" description="">
|
||||
<keyValuePair key="command" value="xsim" description="" />
|
||||
</section>
|
||||
<section name="usage" level="2" order="2" description="">
|
||||
<keyValuePair key="iteration" value="0" description="" />
|
||||
<keyValuePair key="runtime" value="210 ns" description="" />
|
||||
<keyValuePair key="simulation_memory" value="6048_KB" description="" />
|
||||
<keyValuePair key="simulation_time" value="0.03_sec" description="" />
|
||||
<keyValuePair key="trace_waveform" value="true" description="" />
|
||||
</section>
|
||||
</section>
|
||||
</section>
|
||||
</webTalkData>
|
||||
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
|
|
@ -1,41 +0,0 @@
|
|||
[General]
|
||||
ARRAY_DISPLAY_LIMIT=1024
|
||||
RADIX=hex
|
||||
TIME_UNIT=ns
|
||||
TRACE_LIMIT=65536
|
||||
VHDL_ENTITY_SCOPE_FILTER=true
|
||||
VHDL_PACKAGE_SCOPE_FILTER=false
|
||||
VHDL_BLOCK_SCOPE_FILTER=true
|
||||
VHDL_PROCESS_SCOPE_FILTER=false
|
||||
VHDL_PROCEDURE_SCOPE_FILTER=false
|
||||
VERILOG_MODULE_SCOPE_FILTER=true
|
||||
VERILOG_PACKAGE_SCOPE_FILTER=false
|
||||
VERILOG_BLOCK_SCOPE_FILTER=false
|
||||
VERILOG_TASK_SCOPE_FILTER=false
|
||||
VERILOG_PROCESS_SCOPE_FILTER=false
|
||||
INPUT_OBJECT_FILTER=true
|
||||
OUTPUT_OBJECT_FILTER=true
|
||||
INOUT_OBJECT_FILTER=true
|
||||
INTERNAL_OBJECT_FILTER=true
|
||||
CONSTANT_OBJECT_FILTER=true
|
||||
VARIABLE_OBJECT_FILTER=true
|
||||
SCOPE_NAME_COLUMN_WIDTH=75
|
||||
SCOPE_DESIGN_UNIT_COLUMN_WIDTH=75
|
||||
SCOPE_BLOCK_TYPE_COLUMN_WIDTH=75
|
||||
OBJECT_NAME_COLUMN_WIDTH=166
|
||||
OBJECT_VALUE_COLUMN_WIDTH=75
|
||||
OBJECT_DATA_TYPE_COLUMN_WIDTH=75
|
||||
PROCESS_NAME_COLUMN_WIDTH=75
|
||||
PROCESS_TYPE_COLUMN_WIDTH=75
|
||||
FRAME_INDEX_COLUMN_WIDTH=75
|
||||
FRAME_NAME_COLUMN_WIDTH=75
|
||||
FRAME_FILE_NAME_COLUMN_WIDTH=75
|
||||
FRAME_LINE_NUM_COLUMN_WIDTH=166
|
||||
LOCAL_NAME_COLUMN_WIDTH=75
|
||||
LOCAL_VALUE_COLUMN_WIDTH=75
|
||||
INPUT_LOCAL_FILTER=1
|
||||
OUTPUT_LOCAL_FILTER=1
|
||||
INOUT_LOCAL_FILTER=1
|
||||
INTERNAL_LOCAL_FILTER=1
|
||||
CONSTANT_LOCAL_FILTER=1
|
||||
VARIABLE_LOCAL_FILTER=1
|
||||
Binary file not shown.
|
|
@ -1,7 +0,0 @@
|
|||
Running: xsim.dir/RISC_V_IF_ID_TB_behav/xsimk.exe -simmode gui -wdb RISC_V_IF_ID_TB_behav.wdb -simrunnum 0 -socket 56344
|
||||
Design successfully loaded
|
||||
Design Loading Memory Usage: 5248 KB (Peak: 5248 KB)
|
||||
Design Loading CPU Usage: 15 ms
|
||||
Simulation completed
|
||||
Simulation Memory Usage: 6048 KB (Peak: 6048 KB)
|
||||
Simulation CPU Usage: 30 ms
|
||||
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
|
|
@ -1,16 +0,0 @@
|
|||
0.6
|
||||
2018.3
|
||||
Dec 7 2018
|
||||
00:33:28
|
||||
D:/VivadoProjects/RISC_V/RISC_V.sim/sim_1/behav/xsim/glbl.v,1544155481,verilog,,,,glbl,,,,,,,,
|
||||
D:/VivadoProjects/RISC_V/RISC_V.srcs/sources_1/new/ID.v,1605529191,verilog,,D:/VivadoProjects/RISC_V/RISC_V.srcs/sources_1/new/IF.v,,ID,,,,,,,,
|
||||
D:/VivadoProjects/RISC_V/RISC_V.srcs/sources_1/new/IF.v,1605531235,verilog,,D:/VivadoProjects/RISC_V/RISC_V.srcs/sources_1/new/IF_ID_REG.v,,IF,,,,,,,,
|
||||
D:/VivadoProjects/RISC_V/RISC_V.srcs/sources_1/new/IF_ID_REG.v,1605531978,verilog,,D:/VivadoProjects/RISC_V/RISC_V.srcs/sources_1/new/PC.v,,IF_ID_REG,,,,,,,,
|
||||
D:/VivadoProjects/RISC_V/RISC_V.srcs/sources_1/new/PC.v,1605531852,verilog,,D:/VivadoProjects/RISC_V/RISC_V.srcs/sources_1/new/RISC_V_IF_ID.v,,PC,,,,,,,,
|
||||
D:/VivadoProjects/RISC_V/RISC_V.srcs/sources_1/new/RISC_V_IF_ID.v,1605529967,verilog,,D:/VivadoProjects/RISC_V/RISC_V.srcs/sources_1/new/adder.v,,RISC_V_IF_ID,,,,,,,,
|
||||
D:/VivadoProjects/RISC_V/RISC_V.srcs/sources_1/new/RISC_V_IF_ID_TB.v,1605531978,verilog,,,,RISC_V_IF_ID_TB,,,,,,,,
|
||||
D:/VivadoProjects/RISC_V/RISC_V.srcs/sources_1/new/adder.v,1605530932,verilog,,D:/VivadoProjects/RISC_V/RISC_V.srcs/sources_1/new/imm_gen.v,,adder,,,,,,,,
|
||||
D:/VivadoProjects/RISC_V/RISC_V.srcs/sources_1/new/imm_gen.v,1605383352,verilog,,D:/VivadoProjects/RISC_V/RISC_V.srcs/sources_1/new/instruction_memory.v,,imm_gen,,,,,,,,
|
||||
D:/VivadoProjects/RISC_V/RISC_V.srcs/sources_1/new/instruction_memory.v,1605475140,verilog,,D:/VivadoProjects/RISC_V/RISC_V.srcs/sources_1/new/mux2_1.v,,instruction_memory,,,,,,,,
|
||||
D:/VivadoProjects/RISC_V/RISC_V.srcs/sources_1/new/mux2_1.v,1605535170,verilog,,D:/VivadoProjects/RISC_V/RISC_V.srcs/sources_1/new/registers.v,,mux2_1,,,,,,,,
|
||||
D:/VivadoProjects/RISC_V/RISC_V.srcs/sources_1/new/registers.v,1605532387,verilog,,D:/VivadoProjects/RISC_V/RISC_V.srcs/sources_1/new/RISC_V_IF_ID_TB.v,,registers,,,,,,,,
|
||||
|
|
@ -1 +0,0 @@
|
|||
xil_defaultlib=xsim.dir/xil_defaultlib
|
||||
|
|
@ -1,25 +0,0 @@
|
|||
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/VivadoProjects/RISC_V/RISC_V.srcs/sources_1/new/ID.v" into library xil_defaultlib
|
||||
INFO: [VRFC 10-311] analyzing module ID
|
||||
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/VivadoProjects/RISC_V/RISC_V.srcs/sources_1/new/IF.v" into library xil_defaultlib
|
||||
INFO: [VRFC 10-311] analyzing module IF
|
||||
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/VivadoProjects/RISC_V/RISC_V.srcs/sources_1/new/IF_ID_REG.v" into library xil_defaultlib
|
||||
INFO: [VRFC 10-311] analyzing module IF_ID_REG
|
||||
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/VivadoProjects/RISC_V/RISC_V.srcs/sources_1/new/PC.v" into library xil_defaultlib
|
||||
INFO: [VRFC 10-311] analyzing module PC
|
||||
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/VivadoProjects/RISC_V/RISC_V.srcs/sources_1/new/RISC_V_IF_ID.v" into library xil_defaultlib
|
||||
INFO: [VRFC 10-311] analyzing module RISC_V_IF_ID
|
||||
WARNING: [VRFC 10-3676] redeclaration of ansi port 'PC_ID' is not allowed [D:/VivadoProjects/RISC_V/RISC_V.srcs/sources_1/new/RISC_V_IF_ID.v:44]
|
||||
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/VivadoProjects/RISC_V/RISC_V.srcs/sources_1/new/adder.v" into library xil_defaultlib
|
||||
INFO: [VRFC 10-311] analyzing module adder
|
||||
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/VivadoProjects/RISC_V/RISC_V.srcs/sources_1/new/imm_gen.v" into library xil_defaultlib
|
||||
INFO: [VRFC 10-311] analyzing module imm_gen
|
||||
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/VivadoProjects/RISC_V/RISC_V.srcs/sources_1/new/instruction_memory.v" into library xil_defaultlib
|
||||
INFO: [VRFC 10-311] analyzing module instruction_memory
|
||||
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/VivadoProjects/RISC_V/RISC_V.srcs/sources_1/new/mux2_1.v" into library xil_defaultlib
|
||||
INFO: [VRFC 10-311] analyzing module mux2_1
|
||||
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/VivadoProjects/RISC_V/RISC_V.srcs/sources_1/new/registers.v" into library xil_defaultlib
|
||||
INFO: [VRFC 10-311] analyzing module registers
|
||||
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/VivadoProjects/RISC_V/RISC_V.srcs/sources_1/new/RISC_V_IF_ID_TB.v" into library xil_defaultlib
|
||||
INFO: [VRFC 10-311] analyzing module RISC_V_IF_ID_TB
|
||||
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/VivadoProjects/RISC_V/RISC_V.sim/sim_1/behav/xsim/glbl.v" into library xil_defaultlib
|
||||
INFO: [VRFC 10-311] analyzing module glbl
|
||||
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
|
|
@ -1,57 +0,0 @@
|
|||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 11/14/2020 08:22:59 PM
|
||||
// Design Name:
|
||||
// Module Name: ID
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
module ID(input clk,
|
||||
input [31:0] PC_ID, INSTRUCTION_ID, //
|
||||
input RegWrite_WB, //
|
||||
input [31:0] ALU_DATA_WB, //
|
||||
input [4:0] RD_WB, //
|
||||
output [31:0] IMM_ID, //
|
||||
output [31:0] REG_DATA1_ID, REG_DATA2_ID, //
|
||||
output reg [2:0] FUNCT3_ID, //
|
||||
output reg [6:0] FUNCT7_ID, //
|
||||
output reg [6:0] OPCODE_ID, //
|
||||
output reg [4:0] RD_ID, //
|
||||
output reg [4:0] RS1_ID, //
|
||||
output reg [4:0] RS2_ID); //
|
||||
|
||||
always @(*) begin
|
||||
OPCODE_ID <= INSTRUCTION_ID[6:0];
|
||||
RD_ID <= INSTRUCTION_ID[11:7];
|
||||
FUNCT3_ID <= INSTRUCTION_ID[14:12];
|
||||
RS1_ID <= INSTRUCTION_ID[19:15];
|
||||
RS2_ID <= INSTRUCTION_ID[24:20];
|
||||
FUNCT7_ID <= INSTRUCTION_ID[31:25];
|
||||
end
|
||||
|
||||
registers reg0(
|
||||
clk,
|
||||
RegWrite_WB,
|
||||
RS1_ID,
|
||||
RS2_ID,
|
||||
RD_WB,
|
||||
ALU_DATA_WB,
|
||||
REG_DATA1_ID,
|
||||
REG_DATA2_ID
|
||||
);
|
||||
imm_gen imm_gen0(INSTRUCTION_ID, IMM_ID);
|
||||
endmodule
|
||||
|
|
@ -1,36 +0,0 @@
|
|||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 11/02/2020 02:02:33 PM
|
||||
// Design Name:
|
||||
// Module Name: IF
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
module IF(input clk, reset,
|
||||
input PCSrc, PC_write,
|
||||
input [31:0] PC_Branch,
|
||||
output [31:0] PC_IF, INSTRUCTION_IF);
|
||||
|
||||
wire [31:0] PC_4;
|
||||
wire [31:0] PC_MUX;
|
||||
|
||||
PC pc0(clk, reset, PC_write, PC_MUX, PC_IF);
|
||||
instruction_memory instr_mem0(PC_IF[11:2], INSTRUCTION_IF);
|
||||
adder adder0(PC_IF, 32'b0100, PC_4);
|
||||
mux2_1 mux0(PC_4, PC_Branch, PCSrc, PC_MUX);
|
||||
|
||||
endmodule
|
||||
|
|
@ -1,33 +0,0 @@
|
|||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 11/14/2020 09:49:56 PM
|
||||
// Design Name:
|
||||
// Module Name: IF_ID_REG
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
module IF_ID_REG(input clk, reset, write,
|
||||
input [63:0] in,
|
||||
output reg [63:0] out);
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (write)
|
||||
out <= in;
|
||||
if (reset)
|
||||
out <= 0;
|
||||
end
|
||||
endmodule
|
||||
|
|
@ -1,34 +0,0 @@
|
|||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 11/02/2020 12:35:41 PM
|
||||
// Design Name:
|
||||
// Module Name: PC
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
module PC(input clk, res, write,
|
||||
input [31:0] in,
|
||||
output reg [31:0] out);
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (write)
|
||||
out <= in;
|
||||
if (res)
|
||||
out <= 32'b0;
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
|
@ -1,66 +0,0 @@
|
|||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 11/15/2020 01:26:31 PM
|
||||
// Design Name:
|
||||
// Module Name: RISC_V_IF_ID
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
module RISC_V_IF_ID(input clk, reset,
|
||||
input IF_ID_write,
|
||||
input PCSrc, PC_write,
|
||||
input [31:0] PC_Branch,
|
||||
input RegWrite_WB,
|
||||
input [31:0] ALU_DATA_WB,
|
||||
input [4:0] RD_WB,
|
||||
output [31:0] PC_ID,
|
||||
output [31:0] INSTRUCTION_ID,
|
||||
output [31:0] IMM_ID,
|
||||
output [31:0] REG_DATA1_ID,
|
||||
output [31:0] REG_DATA2_ID,
|
||||
output [2:0] FUNCT3_ID,
|
||||
output [6:0] FUNCT7_ID,
|
||||
output [6:0] OPCODE_ID,
|
||||
output [4:0] RD_ID,
|
||||
output [4:0] RS1_ID,
|
||||
output [4:0] RS2_ID
|
||||
);
|
||||
|
||||
wire [31:0] PC_IF, INSTRUCTION_IF;
|
||||
wire [31:0] PC_ID, INSTRUCTION_ID;
|
||||
|
||||
IF if0(clk, reset, PCSrc, PC_write, PC_Branch, PC_IF, INSTRUCTION_IF);
|
||||
IF_ID_REG p0(clk, reset, IF_ID_write, {PC_IF, INSTRUCTION_IF}, {PC_ID, INSTRUCTION_ID});
|
||||
ID id0(
|
||||
clk,
|
||||
PC_ID,
|
||||
INSTRUCTION_ID,
|
||||
RegWrite_WB,
|
||||
ALU_DATA_WB,
|
||||
RD_WB,
|
||||
IMM_ID,
|
||||
REG_DATA1_ID,
|
||||
REG_DATA2_ID,
|
||||
FUNCT3_ID,
|
||||
FUNCT7_ID,
|
||||
OPCODE_ID,
|
||||
RD_ID,
|
||||
RS1_ID,
|
||||
RS2_ID
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
|
@ -1,57 +0,0 @@
|
|||
///////////////////////////////////////TESTBENCH//////////////////////////////////////////////////////////////////
|
||||
module RISC_V_IF_ID_TB;
|
||||
|
||||
reg clk,reset;
|
||||
reg IF_ID_write;
|
||||
reg PCSrc,PC_write;
|
||||
reg [31:0] PC_Branch;
|
||||
reg RegWrite_WB;
|
||||
reg [31:0] ALU_DATA_WB;
|
||||
reg [4:0] RD_WB;
|
||||
wire [31:0] PC_ID;
|
||||
wire [31:0] INSTRUCTION_ID;
|
||||
wire [31:0] IMM_ID;
|
||||
wire [31:0] REG_DATA1_ID,REG_DATA2_ID;
|
||||
wire [2:0] FUNCT3_ID;
|
||||
wire [6:0] FUNCT7_ID;
|
||||
wire [6:0] OPCODE_ID;
|
||||
wire [4:0] RD_ID;
|
||||
wire [4:0] RS1_ID;
|
||||
wire [4:0] RS2_ID;
|
||||
|
||||
RISC_V_IF_ID procesor(clk,reset,
|
||||
IF_ID_write,
|
||||
PCSrc,PC_write,
|
||||
PC_Branch,
|
||||
RegWrite_WB,
|
||||
ALU_DATA_WB,
|
||||
RD_WB,
|
||||
PC_ID,
|
||||
INSTRUCTION_ID,
|
||||
IMM_ID,
|
||||
REG_DATA1_ID,REG_DATA2_ID,
|
||||
FUNCT3_ID,
|
||||
FUNCT7_ID,
|
||||
OPCODE_ID,
|
||||
RD_ID,
|
||||
RS1_ID,
|
||||
RS2_ID);
|
||||
|
||||
always #5 clk=~clk;
|
||||
|
||||
initial begin
|
||||
#0 clk=1'b0;
|
||||
reset=1'b1;
|
||||
|
||||
IF_ID_write = 1'b1;
|
||||
PCSrc = 1'b0;
|
||||
PC_write = 1'b1;
|
||||
PC_Branch = 32'b0;
|
||||
RegWrite_WB = 1'b0;
|
||||
ALU_DATA_WB = 32'b0;
|
||||
RD_WB = 5'b0;
|
||||
|
||||
#10 reset=1'b0;
|
||||
#200 $finish;
|
||||
end
|
||||
endmodule
|
||||
|
|
@ -1,35 +0,0 @@
|
|||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 11/09/2020 02:32:52 PM
|
||||
// Design Name:
|
||||
// Module Name: imm_gen
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
module imm_gen(input [31:0] in, output reg [31:0] out);
|
||||
|
||||
always @(*) begin
|
||||
casex ({in[14:12], in[6:0]})
|
||||
10'bxxx0000011: out <= {{21{in[31]}}, in[30:20]}; // lw
|
||||
10'bxxx0010011: out <= {{21{in[31]}}, in[30:20]}; // addi, ori
|
||||
10'bxxx0100011: out <= {{21{in[31]}}, in[30:25], in[11:7]}; // sw
|
||||
10'bxxx1100011: out <= {{20{in[31]}}, in[7], in[30:25], in[11:8], 1'b0}; // beq
|
||||
default: out <= 32'b0;
|
||||
endcase
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
|
@ -1,45 +0,0 @@
|
|||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 11/09/2020 02:10:45 PM
|
||||
// Design Name:
|
||||
// Module Name: registers
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
module registers(input clk, reg_write,
|
||||
input [4:0] read_reg1, read_reg2, write_reg,
|
||||
input [31:0] write_data,
|
||||
output [31:0] read_data1, read_data2);
|
||||
|
||||
reg [31:0] REG_FILE [0:31];
|
||||
integer i;
|
||||
|
||||
initial begin
|
||||
for (i = 0; i < 32; i = i + 1) begin
|
||||
REG_FILE[i] <= i;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (reg_write && write_reg)
|
||||
REG_FILE[write_reg] <= write_data;
|
||||
end
|
||||
|
||||
assign read_data1 = REG_FILE[read_reg1];
|
||||
assign read_data2 = REG_FILE[read_reg2];
|
||||
|
||||
endmodule
|
||||
253
RISC_V.xpr
253
RISC_V.xpr
|
|
@ -1,253 +0,0 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!-- Product Version: Vivado v2018.3 (64-bit) -->
|
||||
<!-- -->
|
||||
<!-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. -->
|
||||
|
||||
<Project Version="7" Minor="39" Path="D:/VivadoProjects/RISC_V/RISC_V.xpr">
|
||||
<DefaultLaunch Dir="$PRUNDIR"/>
|
||||
<Configuration>
|
||||
<Option Name="Id" Val="ee467e506e3e426b91b11db7a6f036e4"/>
|
||||
<Option Name="Part" Val="xc7k70tfbv676-1"/>
|
||||
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
|
||||
<Option Name="CompiledLibDirXSim" Val=""/>
|
||||
<Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
|
||||
<Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
|
||||
<Option Name="CompiledLibDirIES" Val="$PCACHEDIR/compile_simlib/ies"/>
|
||||
<Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
|
||||
<Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
|
||||
<Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
|
||||
<Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
|
||||
<Option Name="BoardPart" Val=""/>
|
||||
<Option Name="ActiveSimSet" Val="sim_1"/>
|
||||
<Option Name="DefaultLib" Val="xil_defaultlib"/>
|
||||
<Option Name="ProjectType" Val="Default"/>
|
||||
<Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
|
||||
<Option Name="IPCachePermission" Val="read"/>
|
||||
<Option Name="IPCachePermission" Val="write"/>
|
||||
<Option Name="EnableCoreContainer" Val="FALSE"/>
|
||||
<Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
|
||||
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
|
||||
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
|
||||
<Option Name="EnableBDX" Val="FALSE"/>
|
||||
<Option Name="DSAVendor" Val="xilinx"/>
|
||||
<Option Name="DSANumComputeUnits" Val="60"/>
|
||||
<Option Name="WTXSimLaunchSim" Val="63"/>
|
||||
<Option Name="WTModelSimLaunchSim" Val="0"/>
|
||||
<Option Name="WTQuestaLaunchSim" Val="0"/>
|
||||
<Option Name="WTIesLaunchSim" Val="0"/>
|
||||
<Option Name="WTVcsLaunchSim" Val="0"/>
|
||||
<Option Name="WTRivieraLaunchSim" Val="0"/>
|
||||
<Option Name="WTActivehdlLaunchSim" Val="0"/>
|
||||
<Option Name="WTXSimExportSim" Val="0"/>
|
||||
<Option Name="WTModelSimExportSim" Val="0"/>
|
||||
<Option Name="WTQuestaExportSim" Val="0"/>
|
||||
<Option Name="WTIesExportSim" Val="0"/>
|
||||
<Option Name="WTVcsExportSim" Val="0"/>
|
||||
<Option Name="WTRivieraExportSim" Val="0"/>
|
||||
<Option Name="WTActivehdlExportSim" Val="0"/>
|
||||
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
|
||||
<Option Name="XSimRadix" Val="hex"/>
|
||||
<Option Name="XSimTimeUnit" Val="ns"/>
|
||||
<Option Name="XSimArrayDisplayLimit" Val="1024"/>
|
||||
<Option Name="XSimTraceLimit" Val="65536"/>
|
||||
<Option Name="SimTypes" Val="rtl"/>
|
||||
<Option Name="SimTypes" Val="bfm"/>
|
||||
<Option Name="SimTypes" Val="tlm"/>
|
||||
<Option Name="SimTypes" Val="tlm_dpi"/>
|
||||
<Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
|
||||
</Configuration>
|
||||
<FileSets Version="1" Minor="31">
|
||||
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
|
||||
<Filter Type="Srcs"/>
|
||||
<File Path="$PSRCDIR/sources_1/new/ID.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/new/IF.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/new/IF_ID_REG.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/new/PC.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/new/RISC_V_IF_ID.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/new/adder.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/new/imm_gen.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/new/instruction_memory.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/new/mux2_1.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/new/registers.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/new/RISC_V_IF_ID_TB.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="C:/Users/lucii/Downloads/Lucrare2/Lucrare2/code.mem">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopModule" Val="RISC_V_IF_ID_TB"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
|
||||
<Filter Type="Constrs"/>
|
||||
<Config>
|
||||
<Option Name="ConstrsType" Val="XDC"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
|
||||
<Filter Type="Srcs"/>
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopModule" Val="RISC_V_IF_ID_TB"/>
|
||||
<Option Name="TopLib" Val="xil_defaultlib"/>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
<Option Name="TransportPathDelay" Val="0"/>
|
||||
<Option Name="TransportIntDelay" Val="0"/>
|
||||
<Option Name="SrcSet" Val="sources_1"/>
|
||||
<Option Name="Incremental" Val="0"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1">
|
||||
<Filter Type="Utils"/>
|
||||
<Config>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
</FileSets>
|
||||
<Simulators>
|
||||
<Simulator Name="XSim">
|
||||
<Option Name="Description" Val="Vivado Simulator"/>
|
||||
<Option Name="CompiledLib" Val="0"/>
|
||||
</Simulator>
|
||||
<Simulator Name="ModelSim">
|
||||
<Option Name="Description" Val="ModelSim Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Questa">
|
||||
<Option Name="Description" Val="Questa Advanced Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Riviera">
|
||||
<Option Name="Description" Val="Riviera-PRO Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="ActiveHDL">
|
||||
<Option Name="Description" Val="Active-HDL Simulator"/>
|
||||
</Simulator>
|
||||
</Simulators>
|
||||
<Runs Version="1" Minor="10">
|
||||
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7k70tfbv676-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2018"/>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2018"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
</Run>
|
||||
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7k70tfbv676-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2018"/>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2018"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
</Run>
|
||||
</Runs>
|
||||
<Board/>
|
||||
<DashboardSummary Version="1" Minor="0">
|
||||
<Dashboards>
|
||||
<Dashboard Name="default_dashboard">
|
||||
<Gadgets>
|
||||
<Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
|
||||
<GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
|
||||
<GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
|
||||
</Gadget>
|
||||
<Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
|
||||
</Gadget>
|
||||
</Gadgets>
|
||||
</Dashboard>
|
||||
<CurrentDashboard>default_dashboard</CurrentDashboard>
|
||||
</Dashboards>
|
||||
</DashboardSummary>
|
||||
<BootPmcSettings Version="1" Minor="0">
|
||||
<Parameters/>
|
||||
</BootPmcSettings>
|
||||
</Project>
|
||||
|
|
@ -0,0 +1,7 @@
|
|||
00008133 //add x2,x1,x0
|
||||
00108093 //addi x1,x1,1
|
||||
0020F1B3 //and x3,x1,x2
|
||||
0010E213 //ori x4,x1,1
|
||||
0042A223 //sw x4,4(x5)
|
||||
00802603 //lw x12,8(x0)
|
||||
04090E63 //beq x18,x0,5c
|
||||
|
|
@ -0,0 +1,27 @@
|
|||
///////////////////////////////////////TESTBENCH//////////////////////////////////////////////////////////////////
|
||||
module RISC_V_TB;
|
||||
reg clk,reset;
|
||||
wire [31:0] PC_EX, ALU_OUT_EX, PC_MEM;
|
||||
wire PCSrc;
|
||||
wire [31:0] DATA_MEMORY_MEM;
|
||||
wire [31:0] ALU_DATA_WB;
|
||||
wire [1:0] forwardA, forwardB;
|
||||
wire pipeline_stall;
|
||||
|
||||
RISC_V_FINAL risc_v(
|
||||
clk, reset,
|
||||
|
||||
PC_EX,ALU_OUT_EX, PC_MEM,
|
||||
PCSrc, DATA_MEMORY_MEM, ALU_DATA_WB,
|
||||
forwardA, forwardB, pipeline_stall
|
||||
);
|
||||
|
||||
always #5 clk=~clk;
|
||||
|
||||
initial begin
|
||||
#0 clk=1'b0;
|
||||
reset=1'b1;
|
||||
#10 reset=1'b0;
|
||||
#105 $finish;
|
||||
end
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,14 @@
|
|||
/////////////////////////////////////////PC_MODULE///////////////////////////////////////////////////////////////
|
||||
module PC(input clk,res,write,
|
||||
input [31:0] in,
|
||||
output reg [31:0] out);
|
||||
|
||||
always@(posedge clk) begin
|
||||
if(res)
|
||||
out<=32'b0;
|
||||
else if(write)
|
||||
out<=in;
|
||||
end
|
||||
|
||||
endmodule
|
||||
//////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
|
@ -0,0 +1,23 @@
|
|||
////////////////////////////////////////CONTROL_PATH_MODULE///////////////////////////////////////////////////
|
||||
module control_path(input [6:0] opcode,
|
||||
input control_sel,
|
||||
output reg Branch, MemRead,MemtoReg,MemWrite,ALUSrc,RegWrite,
|
||||
output reg [1:0] ALUop);
|
||||
|
||||
always@(opcode) begin
|
||||
if (control_sel)
|
||||
{ALUSrc,MemtoReg,RegWrite,MemRead,MemWrite,Branch,ALUop} <= 8'b00000000;
|
||||
else begin
|
||||
casex(opcode)
|
||||
7'b0000000: {ALUSrc,MemtoReg,RegWrite,MemRead,MemWrite,Branch,ALUop} <= 8'b00000000; //nop from ISA
|
||||
7'b0000011: {ALUSrc,MemtoReg,RegWrite,MemRead,MemWrite,Branch,ALUop} <= 8'b11110000; //lw
|
||||
7'b0100011: {ALUSrc,MemtoReg,RegWrite,MemRead,MemWrite,Branch,ALUop} <= 8'b10001000; //sw
|
||||
7'b0110011: {ALUSrc,MemtoReg,RegWrite,MemRead,MemWrite,Branch,ALUop} <= 8'b00100010; //R32-format
|
||||
7'b0010011: {ALUSrc,MemtoReg,RegWrite,MemRead,MemWrite,Branch,ALUop} <= 8'b10100011; //Register32-Immediate Arithmetic Instructions
|
||||
7'b1100011: {ALUSrc,MemtoReg,RegWrite,MemRead,MemWrite,Branch,ALUop} <= 8'b00000101; //branch instructions
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
//////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
|
@ -0,0 +1,23 @@
|
|||
module IF_ID_reg(clk,reset,write,pc_in,instruction_in,pc_out,instruction_out);
|
||||
|
||||
input clk,write,reset;
|
||||
input [31:0] pc_in;
|
||||
input [31:0] instruction_in;
|
||||
|
||||
output reg [31:0] pc_out;
|
||||
output reg [31:0] instruction_out;
|
||||
|
||||
always@(posedge clk) begin
|
||||
if (reset) begin
|
||||
pc_out<=32'b0;
|
||||
instruction_out<=32'b0;
|
||||
end
|
||||
else begin
|
||||
if(write) begin
|
||||
pc_out <= pc_in;
|
||||
instruction_out <= instruction_in;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,22 @@
|
|||
//////////////////////////////////////////IMM_GEN_MODULE/////////////////////////////////////////////////////
|
||||
module imm_gen(input [31:0] in,
|
||||
output reg [31:0] out);
|
||||
|
||||
always@(*) begin
|
||||
casex({in[14:12],in[6:0]})
|
||||
10'bxxx0000011: out <= {{20{in[31]}},in[31:20]}; //load instructions
|
||||
10'b0000010011: out <= {{20{in[31]}},in[31:20]}; //addi
|
||||
10'b1110010011: out <= {{20{in[31]}},in[31:20]}; //andi
|
||||
10'b1100010011: out <= {{20{in[31]}},in[31:20]}; //ori
|
||||
10'b1000010011: out <= {{20{in[31]}},in[31:20]}; //xori
|
||||
10'b0100010011: out <= {{20{in[31]}},in[31:20]}; //slti
|
||||
10'b0110010011: out <= {{20{in[31]}},in[31:20]}; //sltiu
|
||||
10'b1010010011: out <= {27'b0,in[24:20]}; //srli,srai
|
||||
10'b0010010011: out <= {27'b0,in[24:20]}; //slli
|
||||
10'bxxx0100011: out <= {{20{in[31]}},in[31:25],in[11:7]}; //store instructions
|
||||
10'bxxx1100011: out <= {{19{in[31]}},in[31],in[7],in[30:25],in[11:8], 1'b0}; //beq,bne,blt,bge,bltu,bgeu
|
||||
default: out <= 32'b0;
|
||||
endcase
|
||||
end
|
||||
endmodule
|
||||
//////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
|
@ -0,0 +1,14 @@
|
|||
///////////////////////////////////////INSTRUCTION_MEMORY/////////////////////////////////////////////////////
|
||||
module instruction_memory(input [9:0] address,
|
||||
output reg [31:0] instruction);
|
||||
|
||||
reg [31:0] codeMemory [0:1023];
|
||||
|
||||
initial $readmemh("code.mem", codeMemory);
|
||||
|
||||
always@(address) begin
|
||||
instruction <= codeMemory[address];
|
||||
end
|
||||
|
||||
endmodule
|
||||
//////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
|
@ -0,0 +1,30 @@
|
|||
///////////////////////////////////REGISTER_FILE_MODULE///////////////////////////////////////////////////////
|
||||
module registers(input clk,reg_write,
|
||||
input [4:0] read_reg1,read_reg2,write_reg,
|
||||
input [31:0] write_data,
|
||||
output [31:0] read_data1,read_data2);
|
||||
|
||||
reg [31:0] Registers [0:31];
|
||||
|
||||
integer i;
|
||||
initial begin
|
||||
for (i = 0; i < 32; i = i + 1) begin
|
||||
Registers[i] = i;
|
||||
end
|
||||
end
|
||||
|
||||
always@(posedge clk) begin
|
||||
if(reg_write && write_reg)
|
||||
Registers[write_reg] <= write_data;
|
||||
end
|
||||
|
||||
assign read_data1 = (read_reg1 != 5'b0) ? //it is different from x0
|
||||
(((reg_write == 1'b1)&&(read_reg1 == write_reg)) ?
|
||||
write_data : Registers[read_reg1]) : 32'b0;
|
||||
|
||||
assign read_data2 = (read_reg2 != 5'b0) ? //it is different from x0
|
||||
(((reg_write == 1'b1)&&(read_reg2 == write_reg)) ?
|
||||
write_data : Registers[read_reg2]) : 32'b0;
|
||||
|
||||
endmodule
|
||||
//////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
|
@ -0,0 +1,77 @@
|
|||
//////////////////////////////////////////////RISC-V_MODULE///////////////////////////////////////////////////
|
||||
module RISC_V_IF_ID(input clk,
|
||||
input reset,
|
||||
input control_sel,
|
||||
|
||||
input IF_ID_write,
|
||||
input PCSrc,PC_write,
|
||||
input [31:0] PC_Branch,
|
||||
input RegWrite_WB,
|
||||
input [31:0] ALU_DATA_WB,
|
||||
input [4:0] RD_WB,
|
||||
|
||||
output [31:0] PC_ID,
|
||||
output [31:0] INSTRUCTION_ID,
|
||||
output [31:0] IMM_ID,
|
||||
output [31:0] REG_DATA1_ID,
|
||||
output [31:0] REG_DATA2_ID,
|
||||
|
||||
output [2:0] FUNCT3_ID,
|
||||
output [6:0] FUNCT7_ID,
|
||||
output [6:0] OPCODE_ID,
|
||||
output [4:0] RD_ID,
|
||||
output [4:0] RS1_ID,
|
||||
output [4:0] RS2_ID,
|
||||
|
||||
output RegWrite_ID,
|
||||
output MemtoReg_ID,
|
||||
output MemRead_ID,
|
||||
output MemWrite_ID,
|
||||
output [1:0] ALUop_ID,
|
||||
output ALUSrc_ID,
|
||||
output Branch_ID
|
||||
);
|
||||
|
||||
//////////////////////////////////////////IF signals////////////////////////////////////////////////////////
|
||||
wire [31:0] PC_IF;
|
||||
wire [31:0] INSTRUCTION_IF;
|
||||
|
||||
|
||||
/////////////////////////////////////IF Module/////////////////////////////////////
|
||||
IF instruction_fetch(clk, reset,
|
||||
PCSrc, PC_write,
|
||||
PC_Branch,
|
||||
PC_IF,INSTRUCTION_IF);
|
||||
|
||||
|
||||
//////////////////////////////////////pipeline registers////////////////////////////////////////////////////
|
||||
IF_ID_reg IF_ID_REGISTER(clk,reset,
|
||||
IF_ID_write,
|
||||
PC_IF,INSTRUCTION_IF,
|
||||
PC_ID,INSTRUCTION_ID);
|
||||
|
||||
|
||||
////////////////////////////////////////ID Module//////////////////////////////////
|
||||
ID instruction_decode(clk,
|
||||
control_sel,
|
||||
PC_ID,INSTRUCTION_ID,
|
||||
RegWrite_WB,
|
||||
ALU_DATA_WB,
|
||||
RD_WB,
|
||||
IMM_ID,
|
||||
REG_DATA1_ID,REG_DATA2_ID,
|
||||
FUNCT3_ID,
|
||||
FUNCT7_ID,
|
||||
OPCODE_ID,
|
||||
RD_ID,
|
||||
RS1_ID,
|
||||
RS2_ID,
|
||||
RegWrite_ID,
|
||||
MemtoReg_ID,
|
||||
MemRead_ID,
|
||||
MemWrite_ID,
|
||||
ALUop_ID,
|
||||
ALUSrc_ID,
|
||||
Branch_ID);
|
||||
endmodule
|
||||
///////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
|
@ -0,0 +1,38 @@
|
|||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 12/07/2020 01:33:07 PM
|
||||
// Design Name:
|
||||
// Module Name: ALU
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
module ALU(input [3:0] ALUinput,
|
||||
input [31:0] ina,inb,
|
||||
output reg zero,
|
||||
output reg [31:0] out);
|
||||
|
||||
always @(ina or inb or ALUinput) begin
|
||||
case(ALUinput)
|
||||
4'b0010: out = ina + inb;
|
||||
4'b0110: out = ina - inb;
|
||||
4'b0000: out = ina & inb;
|
||||
4'b0001: out = ina | inb;
|
||||
default: out = 32'hFFFFFFFF;
|
||||
endcase
|
||||
zero <= (out == 0);
|
||||
end
|
||||
endmodule
|
||||
|
||||
|
|
@ -0,0 +1,42 @@
|
|||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 12/07/2020 12:38:23 PM
|
||||
// Design Name:
|
||||
// Module Name: ALUcontrol
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
module ALUcontrol(input [1:0] ALUop,
|
||||
input [6:0] funct7,
|
||||
input [2:0] funct3,
|
||||
output reg [3:0] ALUinput);
|
||||
|
||||
always @(ALUop or funct7 or funct3) begin
|
||||
casex({ALUop, funct7, funct3})
|
||||
12'b00XXXXXXXXXX: ALUinput <= 4'b0010; // ld, sd
|
||||
12'b01XXXXXXXXXX: ALUinput <= 4'b0110; // beq
|
||||
12'b100000000000: ALUinput <= 4'b0010; // add
|
||||
12'b100100000000: ALUinput <= 4'b0110; // sub
|
||||
12'b100000000111: ALUinput <= 4'b0000; // and
|
||||
12'b100000000110: ALUinput <= 4'b0001; // or
|
||||
12'b11xxxxxxx000: ALUinput <= 4'b0010; // addi
|
||||
12'b11xxxxxxx110: ALUinput <= 4'b0001; // ori
|
||||
default: ALUinput <= 4'b1111;
|
||||
endcase
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,37 @@
|
|||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 12/07/2020 12:54:36 PM
|
||||
// Design Name:
|
||||
// Module Name: ALUop
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
module ALU(input [3:0] ALUop,
|
||||
input [31:0] ina,inb,
|
||||
output reg zero,
|
||||
output reg [31:0] out);
|
||||
|
||||
always @(ina or inb or ALUop) begin
|
||||
case(ALUop)
|
||||
4'b0010: out <= ina + inb;
|
||||
4'b0110: out <= ina - inb;
|
||||
4'b0000: out <= ina & inb;
|
||||
4'b0001: out <= ina | inb;
|
||||
endcase
|
||||
zero <= (out == 0);
|
||||
end
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,61 @@
|
|||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 12/07/2020 01:02:51 PM
|
||||
// Design Name:
|
||||
// Module Name: EX
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
module EX(input [31:0] IMM_EX,
|
||||
input [31:0] REG_DATA1_EX,
|
||||
input [31:0] REG_DATA2_EX,
|
||||
input [31:0] PC_EX,
|
||||
input [2:0] FUNCT3_EX,
|
||||
input [6:0] FUNCT7_EX,
|
||||
input [4:0] RD_EX,
|
||||
input [4:0] RS1_EX,
|
||||
input [4:0] RS2_EX,
|
||||
input RegWrite_EX,
|
||||
input MemtoReg_EX,
|
||||
input MemRead_EX,
|
||||
input MemWrite_EX,
|
||||
input [1:0] ALUop_EX,
|
||||
input ALUSrc_EX,
|
||||
input Branch_EX,
|
||||
input [1:0] forwardA,forwardB,
|
||||
|
||||
input [31:0] ALU_DATA_WB,
|
||||
input [31:0] ALU_OUT_MEM,
|
||||
|
||||
output ZERO_EX,
|
||||
output [31:0] ALU_OUT_EX,
|
||||
output [31:0] PC_Branch_EX,
|
||||
output [31:0] REG_DATA2_EX_FINAL
|
||||
);
|
||||
|
||||
wire [3:0] ALUinput;
|
||||
wire [31:0] ALU_OP_1, ALU_OP_2;
|
||||
|
||||
mux4_1 mux0(REG_DATA1_EX, ALU_DATA_WB, ALU_OUT_MEM, 0, forwardA, ALU_OP_1);
|
||||
mux4_1 mux1(REG_DATA2_EX, ALU_DATA_WB, ALU_OUT_MEM, 0, forwardB, REG_DATA2_EX_FINAL);
|
||||
mux2_1 mux2(REG_DATA2_EX_FINAL, IMM_EX, ALUSrc_EX, ALU_OP_2);
|
||||
|
||||
ALUcontrol control0(ALUop_EX, FUNCT7_EX, FUNCT3_EX, ALUinput);
|
||||
ALU alu0(ALUinput, ALU_OP_1, ALU_OP_2, ZERO_EX, ALU_OUT_EX);
|
||||
|
||||
adder adder0(PC_EX, IMM_EX, PC_Branch_EX);
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,68 @@
|
|||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 01/03/2021 01:19:39 PM
|
||||
// Design Name:
|
||||
// Module Name: EX_MEM_REG
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
module EX_MEM_REG(
|
||||
output reg [4:0] RD_MEM,
|
||||
output reg RegWrite_MEM,
|
||||
output reg MemtoReg_MEM,
|
||||
output reg MemRead_MEM,
|
||||
output reg MemWrite_MEM,
|
||||
output reg Branch_MEM,
|
||||
output reg Zero_MEM,
|
||||
output reg [31:0] ALU_OUT_MEM,
|
||||
output reg [31:0] PC_Branch_MEM,
|
||||
output reg [31:0] REG_DATA2_MEM_FINAL,
|
||||
|
||||
input [4:0] RD_EX,
|
||||
input RegWrite_EX,
|
||||
input MemtoReg_EX,
|
||||
input MemRead_EX,
|
||||
input MemWrite_EX,
|
||||
input Branch_EX,
|
||||
input Zero_EX,
|
||||
input [31:0] ALU_OUT_EX,
|
||||
input [31:0] PC_Branch_EX,
|
||||
input [31:0] REG_DATA2_EX_FINAL,
|
||||
|
||||
input clk,
|
||||
input reset
|
||||
);
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (reset) begin
|
||||
{RD_MEM, RegWrite_MEM, MemtoReg_MEM, MemRead_MEM, MemWrite_MEM,
|
||||
Branch_MEM, Zero_MEM, ALU_OUT_MEM, PC_Branch_MEM, REG_DATA2_MEM_FINAL} = 107'b0;
|
||||
end
|
||||
else begin
|
||||
RD_MEM = RD_EX;
|
||||
RegWrite_MEM = RegWrite_EX;
|
||||
MemtoReg_MEM = MemtoReg_EX;
|
||||
MemRead_MEM = MemRead_EX;
|
||||
MemWrite_MEM = MemWrite_EX;
|
||||
Branch_MEM = Branch_EX;
|
||||
Zero_MEM = Zero_EX;
|
||||
ALU_OUT_MEM = ALU_OUT_EX;
|
||||
PC_Branch_MEM = PC_Branch_EX;
|
||||
REG_DATA2_MEM_FINAL = REG_DATA2_EX_FINAL;
|
||||
end
|
||||
end
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,43 @@
|
|||
module ID(input clk,
|
||||
input control_sel,
|
||||
input [31:0] PC_ID,INSTRUCTION_ID,
|
||||
input RegWrite_WB,
|
||||
input [31:0] ALU_DATA_WB,
|
||||
input [4:0] RD_WB,
|
||||
output [31:0] IMM_ID,
|
||||
output [31:0] REG_DATA1_ID,REG_DATA2_ID,
|
||||
output [2:0] FUNCT3_ID,
|
||||
output [6:0] FUNCT7_ID,
|
||||
output [6:0] OPCODE_ID,
|
||||
output [4:0] RD_ID,
|
||||
output [4:0] RS1_ID,
|
||||
output [4:0] RS2_ID,
|
||||
output RegWrite_ID,MemtoReg_ID,MemRead_ID,MemWrite_ID,
|
||||
output [1:0] ALUop_ID,
|
||||
output ALUSrc_ID,
|
||||
output Branch_ID);
|
||||
|
||||
|
||||
assign FUNCT3_ID = INSTRUCTION_ID[14:12];
|
||||
assign FUNCT7_ID = INSTRUCTION_ID[31:25];
|
||||
assign OPCODE_ID = INSTRUCTION_ID[6:0];
|
||||
assign RD_ID = INSTRUCTION_ID[11:7];
|
||||
assign RS1_ID = INSTRUCTION_ID[19:15];
|
||||
assign RS2_ID = INSTRUCTION_ID[24:20];
|
||||
|
||||
control_path CONTROL_PATH_MODULE(OPCODE_ID,
|
||||
control_sel,
|
||||
Branch_ID,MemRead_ID,MemtoReg_ID,
|
||||
MemWrite_ID,ALUSrc_ID,RegWrite_ID,
|
||||
ALUop_ID);
|
||||
|
||||
registers REGISTER_FILE_MODULE(clk,RegWrite_WB,
|
||||
RS1_ID,
|
||||
RS2_ID,
|
||||
RD_WB,
|
||||
ALU_DATA_WB,
|
||||
REG_DATA1_ID,REG_DATA2_ID);
|
||||
|
||||
imm_gen IMM_GEN_MODULE(INSTRUCTION_ID,IMM_ID);
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,105 @@
|
|||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 01/03/2021 03:09:26 PM
|
||||
// Design Name:
|
||||
// Module Name: ID_EX_REG
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
module ID_EX_REG(
|
||||
output reg [31:0] PC_EX,
|
||||
output reg [31:0] IMM_EX,
|
||||
output reg [31:0] REG_DATA1_EX,
|
||||
output reg [31:0] REG_DATA2_EX,
|
||||
output reg [2:0] FUNCT3_EX,
|
||||
output reg [6:0] FUNCT7_EX,
|
||||
output reg [6:0] OPCODE_EX,
|
||||
output reg [4:0] RD_EX,
|
||||
output reg [4:0] RS1_EX,
|
||||
output reg [4:0] RS2_EX,
|
||||
output reg RegWrite_EX,
|
||||
output reg MemtoReg_EX,
|
||||
output reg MemRead_EX,
|
||||
output reg MemWrite_EX,
|
||||
output reg [1:0] ALUop_EX,
|
||||
output reg ALUSrc_EX,
|
||||
output reg Branch_EX,
|
||||
|
||||
input [31:0] PC_ID,
|
||||
input [31:0] IMM_ID,
|
||||
input [31:0] REG_DATA1_ID,
|
||||
input [31:0] REG_DATA2_ID,
|
||||
input [2:0] FUNCT3_ID,
|
||||
input [6:0] FUNCT7_ID,
|
||||
input [6:0] OPCODE_ID,
|
||||
input [4:0] RD_ID,
|
||||
input [4:0] RS1_ID,
|
||||
input [4:0] RS2_ID,
|
||||
input RegWrite_ID,
|
||||
input MemtoReg_ID,
|
||||
input MemRead_ID,
|
||||
input MemWrite_ID,
|
||||
input [1:0] ALUop_ID,
|
||||
input ALUSrc_ID,
|
||||
input Branch_ID,
|
||||
|
||||
input clk,
|
||||
input reset
|
||||
);
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (reset) begin
|
||||
PC_EX = 0;
|
||||
IMM_EX = 0;
|
||||
REG_DATA1_EX = 0;
|
||||
REG_DATA2_EX = 0;
|
||||
FUNCT3_EX = 0;
|
||||
FUNCT7_EX = 0;
|
||||
OPCODE_EX = 0;
|
||||
RD_EX = 0;
|
||||
RS1_EX = 0;
|
||||
RS2_EX = 0;
|
||||
RegWrite_EX = 0;
|
||||
MemtoReg_EX = 0;
|
||||
MemRead_EX = 0;
|
||||
MemWrite_EX = 0;
|
||||
ALUop_EX = 0;
|
||||
ALUSrc_EX = 0;
|
||||
Branch_EX = 0;
|
||||
end
|
||||
else begin
|
||||
PC_EX = PC_ID;
|
||||
IMM_EX = IMM_ID;
|
||||
REG_DATA1_EX = REG_DATA1_ID;
|
||||
REG_DATA2_EX = REG_DATA2_ID;
|
||||
FUNCT3_EX = FUNCT3_ID;
|
||||
FUNCT7_EX = FUNCT7_ID;
|
||||
OPCODE_EX = OPCODE_ID;
|
||||
RD_EX = RD_ID;
|
||||
RS1_EX = RS1_ID;
|
||||
RS2_EX = RS2_ID;
|
||||
RegWrite_EX = RegWrite_ID;
|
||||
MemtoReg_EX = MemtoReg_ID;
|
||||
MemRead_EX = MemRead_ID;
|
||||
MemWrite_EX = MemWrite_ID;
|
||||
ALUop_EX = ALUop_ID;
|
||||
ALUSrc_EX = ALUSrc_ID;
|
||||
Branch_EX = Branch_ID;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,22 @@
|
|||
module IF(input clk, reset,
|
||||
input PCSrc, PC_write,
|
||||
input [31:0] PC_Branch,
|
||||
output [31:0] PC_IF,INSTRUCTION_IF);
|
||||
|
||||
wire [9:0] instruction_address = PC_IF[11:2];
|
||||
wire [31:0] PC_MUX;
|
||||
wire [31:0] PC_4_IF;
|
||||
|
||||
PC PC_MODULE(clk,reset,PC_write,PC_MUX,PC_IF);
|
||||
|
||||
instruction_memory INSTRUCTION_MEMORY_MODULE(instruction_address,INSTRUCTION_IF);
|
||||
|
||||
adder ADDER_PC_4_IF(PC_IF,32'b0100,PC_4_IF);
|
||||
|
||||
mux2_1 MUX_PC(PC_4_IF,
|
||||
PC_Branch,
|
||||
PCSrc,
|
||||
PC_MUX);
|
||||
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,57 @@
|
|||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 01/03/2021 01:51:54 PM
|
||||
// Design Name:
|
||||
// Module Name: MEM
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
module MEM(
|
||||
input clk,
|
||||
input [4:0] RD_MEM,
|
||||
input RegWrite_MEM,
|
||||
input MemtoReg_MEM,
|
||||
input MemRead_MEM,
|
||||
input MemWrite_MEM,
|
||||
input Branch_MEM,
|
||||
|
||||
input Zero_MEM,
|
||||
input [31:0] ALU_OUT_MEM,
|
||||
input [31:0] PC_Branch_MEM,
|
||||
input [31:0] REG_DATA2_MEM_FINAL,
|
||||
|
||||
output reg PCSrc_IF,
|
||||
output reg [31:0] PC_Branch_IF,
|
||||
|
||||
output [31:0] READ_DATA
|
||||
);
|
||||
|
||||
data_memory data_memory0(
|
||||
clk,
|
||||
MemRead_MEM,
|
||||
MemWrite_MEM,
|
||||
ALU_OUT_MEM,
|
||||
REG_DATA2_MEM_FINAL,
|
||||
READ_DATA
|
||||
);
|
||||
|
||||
always @(Zero_MEM or Branch_MEM or PC_Branch_MEM) begin
|
||||
PCSrc_IF = Zero_MEM & Branch_MEM;
|
||||
PC_Branch_IF = PC_Branch_MEM;
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,50 @@
|
|||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 01/03/2021 02:22:35 PM
|
||||
// Design Name:
|
||||
// Module Name: MEM_WB_REG
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
module MEM_WB_REG(
|
||||
output reg MemtoReg_WB,
|
||||
output reg RegWrite_WB,
|
||||
output reg [31:0] READ_DATA_WB,
|
||||
output reg [31:0] ALU_RESULT_WB,
|
||||
output reg [4:0] RD_WB,
|
||||
|
||||
input MemtoReg_MEM,
|
||||
input RegWrite_MEM,
|
||||
input [31:0] READ_DATA_MEM,
|
||||
input [31:0] ALU_RESULT_MEM,
|
||||
input [4:0] RD_MEM,
|
||||
|
||||
input clk,
|
||||
input reset
|
||||
);
|
||||
always @(posedge clk) begin
|
||||
if (reset)
|
||||
{MemtoReg_WB, RegWrite_WB, READ_DATA_WB, ALU_RESULT_WB, RD_WB} = 71'b0;
|
||||
else begin
|
||||
MemtoReg_WB = MemtoReg_MEM;
|
||||
RegWrite_WB = RegWrite_MEM;
|
||||
READ_DATA_WB = READ_DATA_MEM;
|
||||
ALU_RESULT_WB = ALU_RESULT_MEM;
|
||||
RD_WB = RD_MEM;
|
||||
end
|
||||
end
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,215 @@
|
|||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 01/03/2021 02:45:33 PM
|
||||
// Design Name:
|
||||
// Module Name: RISC_V_FINAL
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
module RISC_V_FINAL(
|
||||
input clk,
|
||||
input reset,
|
||||
|
||||
output [31:0] PC_EX,
|
||||
output [31:0] ALU_OUT_EX,
|
||||
output [31:0] PC_MEM,
|
||||
output PCSrc,
|
||||
output [31:0] DATA_MEMORY_MEM,
|
||||
output [31:0] ALU_DATA_WB,
|
||||
output [1:0] forwardA, forwardB,
|
||||
output pipeline_stall
|
||||
);
|
||||
|
||||
wire IF_ID_write;
|
||||
wire PC_write;
|
||||
|
||||
wire [31:0] PC_ID;
|
||||
wire [31:0] INSTRUCTION_ID;
|
||||
wire [31:0] IMM_ID;
|
||||
wire [31:0] REG_DATA1_ID;
|
||||
wire [31:0] REG_DATA2_ID;
|
||||
wire [2:0] FUNCT3_ID;
|
||||
wire [6:0] FUNCT7_ID;
|
||||
wire [6:0] OPCODE_ID;
|
||||
wire [4:0] RD_ID;
|
||||
wire [4:0] RS1_ID;
|
||||
wire [4:0] RS2_ID;
|
||||
|
||||
wire RegWrite_ID;
|
||||
wire MemtoReg_ID;
|
||||
wire MemRead_ID;
|
||||
wire MemWrite_ID;
|
||||
wire [1:0] ALUop_ID;
|
||||
wire ALUSrc_ID;
|
||||
wire Branch_ID;
|
||||
|
||||
wire [31:0] IMM_EX;
|
||||
wire [31:0] REG_DATA1_EX;
|
||||
wire [31:0] REG_DATA2_EX;
|
||||
wire [2:0] FUNCT3_EX;
|
||||
wire [6:0] FUNCT7_EX;
|
||||
wire [6:0] OPCODE_EX;
|
||||
wire [4:0] RD_EX;
|
||||
wire [4:0] RS1_EX;
|
||||
wire [4:0] RS2_EX;
|
||||
|
||||
wire RegWrite_EX;
|
||||
wire MemtoReg_EX;
|
||||
wire MemRead_EX;
|
||||
wire MemWrite_EX;
|
||||
wire [1:0] ALUop_EX;
|
||||
wire ALUSrc_EX;
|
||||
wire Branch_EX;
|
||||
|
||||
wire ZERO_EX;
|
||||
wire [31:0] PC_Branch_EX;
|
||||
wire [31:0] REG_DATA2_EX_FINAL;
|
||||
|
||||
wire [4:0] RD_MEM;
|
||||
wire RegWrite_MEM;
|
||||
wire MemtoReg_MEM;
|
||||
wire MemRead_MEM;
|
||||
wire MemWrite_MEM;
|
||||
wire Branch_MEM;
|
||||
|
||||
wire ZERO_MEM;
|
||||
wire [31:0] ALU_OUT_MEM;
|
||||
wire [31:0] PC_Branch_MEM;
|
||||
wire [31:0] REG_DATA2_MEM_FINAL;
|
||||
|
||||
wire [4:0] RD_WB;
|
||||
wire RegWrite_WB;
|
||||
wire MemtoReg_WB;
|
||||
wire [31:0] ALU_OUT_WB;
|
||||
wire [31:0] DATA_MEMORY_WB;
|
||||
|
||||
RISC_V_IF_ID if_id(
|
||||
clk, reset, pipeline_stall,
|
||||
IF_ID_write, PCSrc, PC_write,
|
||||
PC_MEM, RegWrite_WB, ALU_DATA_WB, RD_WB,
|
||||
|
||||
PC_ID, INSTRUCTION_ID, IMM_ID,
|
||||
REG_DATA1_ID, REG_DATA2_ID,
|
||||
|
||||
FUNCT3_ID, FUNCT7_ID, OPCODE_ID,
|
||||
RD_ID, RS1_ID, RS2_ID,
|
||||
|
||||
RegWrite_ID,
|
||||
MemtoReg_ID,
|
||||
MemRead_ID,
|
||||
MemWrite_ID,
|
||||
ALUop_ID,
|
||||
ALUSrc_ID,
|
||||
Branch_ID
|
||||
);
|
||||
|
||||
hazard_detection hazard(RD_EX, RS1_ID, RS2_ID, MemRead_EX, PC_write, IF_ID_write, pipeline_stall);
|
||||
|
||||
ID_EX_REG id_ex_reg(
|
||||
PC_EX, IMM_EX, REG_DATA1_EX,
|
||||
REG_DATA2_EX, FUNCT3_EX, FUNCT7_EX,
|
||||
OPCODE_EX, RD_EX, RS1_EX, RS2_EX,
|
||||
|
||||
RegWrite_EX, MemtoReg_EX,
|
||||
MemRead_EX, MemWrite_EX, ALUop_EX,
|
||||
ALUSrc_EX, Branch_EX,
|
||||
|
||||
PC_ID, IMM_ID, REG_DATA1_ID,
|
||||
REG_DATA2_ID, FUNCT3_ID, FUNCT7_ID,
|
||||
OPCODE_ID, RD_ID, RS1_ID, RS2_ID,
|
||||
|
||||
RegWrite_ID, MemtoReg_ID,
|
||||
MemRead_ID, MemWrite_ID, ALUop_ID,
|
||||
ALUSrc_ID, Branch_ID,
|
||||
|
||||
clk, reset
|
||||
);
|
||||
|
||||
forwarding forward(
|
||||
RS1_EX,
|
||||
RS2_EX,
|
||||
RD_MEM,
|
||||
RD_WB,
|
||||
RegWrite_MEM,
|
||||
RegWrite_WB,
|
||||
forwardA, forwardB
|
||||
);
|
||||
|
||||
EX ex(
|
||||
IMM_EX, REG_DATA1_EX, REG_DATA2_EX,
|
||||
PC_EX, FUNCT3_EX, FUNCT7_EX,
|
||||
RD_EX, RS1_EX, RS2_EX,
|
||||
|
||||
RegWrite_EX, MemtoReg_EX, MemRead_EX,
|
||||
MemWrite_EX, ALUop_EX, ALUSrc_EX,
|
||||
Branch_EX,
|
||||
|
||||
forwardA, forwardB,
|
||||
|
||||
ALU_DATA_WB,
|
||||
ALU_OUT_MEM,
|
||||
|
||||
ZERO_EX,
|
||||
ALU_OUT_EX,
|
||||
PC_Branch_EX,
|
||||
REG_DATA2_EX_FINAL
|
||||
);
|
||||
|
||||
EX_MEM_REG ex_mem_reg(
|
||||
RD_MEM, RegWrite_MEM, MemtoReg_MEM,
|
||||
MemRead_MEM, MemWrite_MEM, Branch_MEM,
|
||||
|
||||
ZERO_MEM, ALU_OUT_MEM, PC_Branch_MEM,
|
||||
REG_DATA2_MEM_FINAL,
|
||||
|
||||
RD_EX, RegWrite_EX, MemtoReg_EX,
|
||||
MemRead_EX, MemWrite_EX, Branch_EX,
|
||||
|
||||
ZERO_EX, ALU_OUT_EX, PC_Branch_EX,
|
||||
REG_DATA2_EX_FINAL,
|
||||
|
||||
clk, reset
|
||||
);
|
||||
|
||||
MEM mem(clk,
|
||||
RD_MEM, RegWrite_MEM, MemtoReg_MEM,
|
||||
MemRead_MEM, MemWrite_MEM, Branch_MEM,
|
||||
|
||||
ZERO_MEM, ALU_OUT_MEM, PC_Branch_MEM,
|
||||
REG_DATA2_MEM_FINAL,
|
||||
|
||||
PCSrc, PC_MEM,
|
||||
|
||||
DATA_MEMORY_MEM
|
||||
);
|
||||
|
||||
MEM_WB_REG mem_wb_reg(
|
||||
MemtoReg_WB, RegWrite_WB, DATA_MEMORY_WB,
|
||||
ALU_OUT_WB, RD_WB,
|
||||
|
||||
MemtoReg_MEM, RegWrite_MEM, DATA_MEMORY_MEM,
|
||||
ALU_OUT_MEM, RD_MEM,
|
||||
|
||||
clk, reset
|
||||
);
|
||||
|
||||
WB wb(
|
||||
MemtoReg_WB, DATA_MEMORY_WB,
|
||||
ALU_OUT_WB,
|
||||
|
||||
ALU_DATA_WB
|
||||
);
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,11 @@
|
|||
module WB(
|
||||
input MemtoReg_WB,
|
||||
input [31:0] READ_DATA_WB,
|
||||
input [31:0] ALU_RESULT_WB,
|
||||
|
||||
output [31:0] ALU_DATA_WB
|
||||
);
|
||||
|
||||
mux2_1 mux0(ALU_RESULT_WB, READ_DATA_WB, MemtoReg_WB, ALU_DATA_WB);
|
||||
|
||||
endmodule
|
||||
|
|
@ -3,7 +3,7 @@
|
|||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 11/02/2020 01:47:57 PM
|
||||
// Create Date: 12/14/2020 02:13:52 PM
|
||||
// Design Name:
|
||||
// Module Name: adder
|
||||
// Project Name:
|
||||
|
|
@ -20,9 +20,6 @@
|
|||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
module adder(input [31:0] ina, inb,
|
||||
output [31:0] out);
|
||||
|
||||
assign out = ina + inb;
|
||||
|
||||
module adder(input [31:0] ina, input [31:0] inb, output reg [31:0] out);
|
||||
always @(ina or inb) out = ina + inb;
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,49 @@
|
|||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 12/14/2020 02:30:26 PM
|
||||
// Design Name:
|
||||
// Module Name: data_memory
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
module data_memory(input clk,
|
||||
input mem_read,
|
||||
input mem_write,
|
||||
input [31:0] address,
|
||||
input [31:0] write_data,
|
||||
output reg [31:0] read_data
|
||||
);
|
||||
|
||||
reg [31:0] RAM [0:1023];
|
||||
integer i;
|
||||
|
||||
initial begin
|
||||
for (i = 0; i < 1024; i = i + 1)
|
||||
RAM[i] = i;
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (mem_write)
|
||||
RAM[address] <= write_data;
|
||||
end
|
||||
|
||||
always @* begin
|
||||
if (mem_read)
|
||||
read_data <= RAM[address];
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,46 @@
|
|||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 12/14/2020 03:02:08 PM
|
||||
// Design Name:
|
||||
// Module Name: forwarding
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
module forwarding(input [4:0] rs1,
|
||||
input [4:0] rs2,
|
||||
input [4:0] ex_mem_rd,
|
||||
input [4:0] mem_wb_rd,
|
||||
input ex_mem_regwrite,
|
||||
input mem_wb_regwrite,
|
||||
output reg [1:0] forwardA,forwardB);
|
||||
|
||||
always @(rs1 or rs2 or ex_mem_rd or mem_wb_rd or ex_mem_regwrite or mem_wb_regwrite) begin
|
||||
forwardA <= 2'b00;
|
||||
forwardB <= 2'b00;
|
||||
|
||||
if (ex_mem_regwrite && ex_mem_rd != 0 && ex_mem_rd == rs1)
|
||||
forwardA <= 2'b10;
|
||||
if (ex_mem_regwrite && ex_mem_rd != 0 && ex_mem_rd == rs2)
|
||||
forwardB <= 2'b10;
|
||||
|
||||
if (mem_wb_regwrite && mem_wb_rd != 0 && !(ex_mem_regwrite && ex_mem_rd != 0 && ex_mem_rd == rs1) && mem_wb_rd == rs1)
|
||||
forwardA <= 2'b01;
|
||||
if (mem_wb_regwrite && mem_wb_rd != 0 && !(ex_mem_regwrite && ex_mem_rd != 0 && ex_mem_rd == rs2) && mem_wb_rd == rs2)
|
||||
forwardB <= 2'b01;
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,38 @@
|
|||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 12/14/2020 02:40:31 PM
|
||||
// Design Name:
|
||||
// Module Name: hazard_detection
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
module hazard_detection(input [4:0] rd,
|
||||
input [4:0] rs1,
|
||||
input [4:0] rs2,
|
||||
input MemRead,
|
||||
output reg PCwrite,
|
||||
output reg IF_IDwrite,
|
||||
output reg control_sel);
|
||||
|
||||
always @(rd or rs1 or rs2 or MemRead) begin
|
||||
if (MemRead && (rd == rs1 || rd == rs2))
|
||||
{PCwrite, IF_IDwrite, control_sel} <= 3'b001;
|
||||
else
|
||||
{PCwrite, IF_IDwrite, control_sel} <= 3'b110;
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
|
@ -3,7 +3,7 @@
|
|||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 11/02/2020 12:32:59 PM
|
||||
// Create Date: 12/14/2020 02:24:05 PM
|
||||
// Design Name:
|
||||
// Module Name: mux2_1
|
||||
// Project Name:
|
||||
|
|
@ -21,11 +21,9 @@
|
|||
|
||||
|
||||
module mux2_1(
|
||||
input [31:0] ina,
|
||||
input [31:0] inb,
|
||||
input [31:0] a, b,
|
||||
input sel,
|
||||
output [31:0] out
|
||||
);
|
||||
|
||||
assign out = sel ? inb : ina;
|
||||
);
|
||||
assign out = (sel) ? b : a;
|
||||
endmodule
|
||||
|
|
@ -3,9 +3,9 @@
|
|||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 11/02/2020 12:42:24 PM
|
||||
// Create Date: 12/07/2020 01:25:06 PM
|
||||
// Design Name:
|
||||
// Module Name: instruction_memory
|
||||
// Module Name: mux4_1
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
|
|
@ -20,14 +20,17 @@
|
|||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
module instruction_memory(input [9:0] address,
|
||||
output reg [31:0] instruction);
|
||||
|
||||
reg [31:0] memory[0:6];
|
||||
|
||||
initial $readmemh("code.mem", memory);
|
||||
|
||||
always @(address)
|
||||
instruction <= memory[address];
|
||||
|
||||
module mux4_1(input [31:0] a, b, c, d,
|
||||
input [1:0] sel,
|
||||
output reg [31:0] out);
|
||||
|
||||
always @(a or b or c or d or sel) begin
|
||||
case (sel)
|
||||
2'b00: out <= a;
|
||||
2'b01: out <= b;
|
||||
2'b10: out <= c;
|
||||
2'b11: out <= d;
|
||||
endcase
|
||||
end
|
||||
|
||||
endmodule
|
||||
Loading…
Reference in New Issue